ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 46

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
4 Hardware Architecture
Power Management Examples with the PLL
The following examples show the more significant options for reducing power dissipation if operation with the PLL
clock synthesizer is desired.
Standard Sleep Mode, PLL Running. This mode would be entered in the same manner as without the PLL. While
the input to the clock synthesizer, CKI, remains running, the alf register's AWAIT bit is set. The PLL will continue to
run and dissipate power. Peripheral units may be turned off to further reduce the sleep power.
sleep:a0 = 0x8000
cont: . . .
Sleep with Slow Internal Clock, PLL Running. In this case, the ring oscillator is selected to clock the processor
before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program
execution.
sleep:a0 = 0x8000
cont: . . .
44
powerc = 0x00F0
do 1 {
alf = a0
nop
}
nop
nop
powerc = 0x0
powerc = 0x40F0
2*nop
do 1 {
alf = a0
nop
}
nop
nop
powerc = 0x00F0
2*nop
powerc = 0x0000
/* Turn off peripherals, core running with PLL */
/* Set alf register in cache loop if running from */
/* external memory with >1 wait state */
/* Stop internal processor clock, interrupt circuits */
/* active */
/* Needed for bedtime execution. Only sleep power plus PLL */
/* power consumed here.... Interrupt wakes up the device */
/* User code executes here */
/* Turn peripheral units back on */
/* Turn off peripherals and select slow clock */
/* Wait for slow clock to take effect */
/* Set alf register in cache loop if running from */
/* external memory with >1 wait state */
/* Stop internal processor clock, interrupt circuits */
/* active */
/* Needed for bedtime execution. Reduced sleep power, PLL */
/* power, and ring oscillator power consumed here... */
/* Interrupt wakes up the device */
/* User code executes here */
/* Select high-speed PLL based clock */
/* Wait for it to take effect */
/* Turn peripheral units back on */
(continued)
Lucent Technologies Inc.
February 1997