ics9248-107 Integrated Device Technology, ics9248-107 Datasheet

no-image

ics9248-107

Manufacturer Part Number
ics9248-107
Description
Frequency Timing Generator For Pentium Ii Systems
Manufacturer
Integrated Device Technology
Datasheet
Frequency Timing Generator for PENTIUM II Systems
Recommended Application:
RCC chipset
Output Features:
Features:
Key Specifications:
9248-107 RevA - 5/21/01
4 - CPUs @ 2.5V, up to 180MHz.
3 - IOAPIC @ 2.5V
3 - 3V66MHz @ 3.3V.
11 - PCIs @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz, @ 3.3V
Up to 180MHz frequency support
Use a zero delay buffer such as the ICS9179-06 to
generate SDRAM clocks.
Support power management: Power down Mode
from I
Spread spectrum for EMI control
Uses external 14.318MHz crystal
5 - FS pins for frequency select
CPU Output Jitter: <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <580ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ = 1.3ns)
CPU to PCI Output Offset: 0.0 - 1.5ns (typ = 1.0ns)
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ = 2.0ns)
± 0.25% center spread).
2
C programming.
Integrated
Circuit
Systems, Inc.
I C
2
SEL24_48#
*SEL24_48#/REF1
{
*FS0/PCICLK_F
FS(4:0)
*FS1/PCICLK1
*FS2/PCICLK2
*FS3/PCICLK3
SDATA
*120K ohm pull-up to VDD on indicated inputs.
SCLK
PD#
PCICLK10
X2
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
X1
GNDREF
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9
VDDREF
GNDPCI
GNDPCI
GNDPCI
VDDPCI
VDDPCI
VDDPCI
REF0
PD#
X1
X2
Block Diagram
XTAL
OSC
Pin Configuration
Spectrum
PLL2
Spread
Control
Config.
PLL1
Logic
Reg.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin SSOP
1
2
3
4
5
6
7
8
9
DIVDER
DIVDER
DIVDER
DIVDER
IOAPIC
3V66
CPU
PCI
/ 2
ICS9248-107
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC0
IOAPIC1
GNDLAPIC
IOAPIC2
VDDLCPU
CPUCLK0
GNDLCPU
CPUCLK1
VDDLCPU
CPUCLK2
CPUCLK3
GNDLCPU
VDD66
3V66_0
3V66_1
3V66_2
GND66
SDATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48
{
48MHz
24_48MHz
IOAPIC (2:0)
PCICLK (10:0)
PCICLK_F
3V66 (2:0)
CPUCLK (3:0)
REF(1:0)
I C
2

Related parts for ics9248-107

ics9248-107 Summary of contents

Page 1

... PCI Output Skew: <580ps • 3V66 Output Skew <250ps • CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ = 1.3ns) • CPU to PCI Output Offset: 0.0 - 1.5ns (typ = 1.0ns) • CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ = 2.0ns) 9248-107 RevA - 5/21/01 ICS9248-107 Pin Configuration GNDREF 1 48 REF0 2 47 *SEL24_48#/REF1 3 ...

Page 2

... ICS9248-107 General Description The ICS9248-107 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a zero delay buffer such as the ICS9179-06. Spread Spectrum may be enabled through I EMI qualification without resorting to board design iterations or costly shielding ...

Page 3

... CPU PC I 3V66 IOAPIC 103.0 34.33 68.67 17.17 100.0 33.33 66.67 16.67 100.5 33.48 66.97 16.74 100.9 33.63 67.27 16.82 107.1 35.70 71.40 17.85 109.0 36.33 72.67 18.17 112.0 37.33 74.67 18.67 114.0 28.50 57.00 14.25 116.0 29.00 58.00 14.50 118.0 29.50 59.00 14.75 133.3 33.33 66.65 16.66 120.0 30.00 60.00 15.00 122.0 30.50 61.00 15.25 125.0 31.25 62.50 15.63 50.0 16.67 33.33 8.33 66.7 16.67 33.33 8.33 133.3 33.33 66.67 16.67 133.9 33.48 66.95 16.74 138 34.5 69 17.25 142 35.5 71 17.75 146 36.5 73 18.25 150 37.5 75 18.75 153 38.25 76.5 19.13 156 39 78 19.5 159.1 39.78 79.55 19.89 162 40.5 81 20.25 166.7 41.67 83.33 20.83 168 171 42.75 85.5 21.38 174 43.5 87 21.75 177 44.25 88.5 22.13 180 45 90 22.5 3 ICS9248-107 ...

Page 4

... ICS9248-107 Serial Configuration Command Bitmap Byte 0: Functionality and frequency select register (Default = ...

Page 5

... Note: Don’t write into this register, writing into this register can cause malfunction 5 ICS9248-107 ...

Page 6

... ICS9248-107 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 7

... 1.25 V CPU frequency < 142 MHz 1.25 V CPU frequency > 142 MHz 1. 1. ICS9248-107 Measurement Points CPU @ 1.25V, 3V66 @ 1.5 V CPU @ 1.25V, PCI @ 1.5 V CPU @ 1.25V, IOAPIC @ 1.25 V MIN TYP MAX UNITS 2 2.3 V 0.3 0.4 V -35 - 0.4 1.03 1.6 ns ...

Page 8

... ICS9248-107 Electrical Characteristics - 3V66 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle Skew T sk1 1 t Jitter, Cycle-to-cycle ...

Page 9

... 2.0 V OH5 0.8 V OL5 0 2 2. 1.5 V jcyc-cyc5 T 9 ICS9248-107 MIN TYP MAX UNITS 2.6 2.9 V 0.3 0.4 V - 314 500 ps MIN TYP MAX UNITS 2.6 2.9 V 0.3 0.4 V -27 -22 ...

Page 10

... ICS9248-107 Electrical Characteristics - IOAPIC 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH4B Output Low Voltage V OL4B Output High Current I OH4B Output Low Current I OL4B 1 Rise Time t r4B 1 Fall Time t f4B 1 Duty Cycle d t4B 1 tsk4B Skew 1 t Jitter, Cycle-to-cycle ...

Page 11

... ICS9248-107 ...

Page 12

... ICS9248-107 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...

Page 13

... As shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 13 ICS9248-107 ...

Page 14

... ICS9248-107 INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS9248yF-107 Example: ICS XXXX PPP Pattern Number ( digit number for parts with ROM code patterns) ...

Related keywords