ics9248-107 Integrated Device Technology, ics9248-107 Datasheet - Page 2

• Manufacturer Part Number: ics9248-107
• Description: Frequency Timing Generator For Pentium Ii Systems
• Manufacturer: Integrated Device Technology

General Description
ICS9248-107
The ICS9248-107 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a zero delay buffer such as the ICS9179-06.
Spread Spectrum may be enabled through I
EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-107 employs a proprietary
closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Descriptions
1, 7, 13, 19, 25, 31 GND
14, 15, 17, 18, 20,
37, 38, 40, 42
4, 10, 16, 23,
Pin number
32, 33, 34
44, 46, 47
36, 41
39, 43
28, 35
21, 22
11
12
24
26
27
29
30
45
48
2
3
5
6
8
9
REF0
REF1
SEL24_48#
VDD
X1
X2
PCICLK_F
FS0
PCICLK1
FS1
PCICLK2
FS2
PCICLK3
FS3
PCICLK (4:10)
PD#
24_48MHz
48MHz
FS4
SCLK
SDATA
3V66(2:0)
GNDLCPU
CPUCLK(3:0)
VDDLCPU
GNDLAPIC
IOAPIC(2:0)
VDDLAPIC
Pin name
2
C. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies
Type
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PWR
OUT
PWR
PWR
OUT
PWR
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
Ground pins
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
Power pins 3.3V
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Free running PCI clock at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output at 3.3V
Logic - input for frequency selection
Clock input of I
Data pin for I2C circuitry 5V tolerant
3.3V clock outputs.
Ground pins for CPUCLKs
Host bus clock output at 2.5V.
Power pins for CPUCLKs. 2.5V
Ground pin for the IOAPIC outputs.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
2
2
C input
Description