pca24s08a NXP Semiconductors, pca24s08a Datasheet - Page 4

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pca24s08a

Manufacturer Part Number
pca24s08a
Description
1024 ? 8-bit Cmos Eeprom With Access Protection
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
6. Functional description
PCA24S08A_1
Product data sheet
6.2.1 Byte/word write
5.2 Pin description
6.1 Device addressing
6.2 Write operations
Table 2.
Refer to
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA24S08A is shown in
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1
in the slave address represent the 2 most significant bits of the word to be addressed. The
third device address bit in the I
standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h
through AFh (hex) are used to access the memory on the chip.
Write operations on the device can be performed only when WP is held LOW. When the
WP pin is held HIGH, content of the full memory is protected (Block 0 to Block 7,
APP registers, ID Page), and no write operation is allowed.
Write command may be used to set the address for a subsequent Read command. For a
write operation, the PCA24S08A requires a second address field. The address field
associated with the two software selectable bits in the slave address is a word address
providing access to the 1024 bytes of memory, as shown in
word address, the PCA24S08A responds with an acknowledge and awaits the next 8 bits
of data, again responding with an acknowledge. Word address is automatically
incremented.
Symbol
n.c.
PROT
V
SDA
SCL
WP
V
Fig 4.
SS
DD
Figure 1 “Block
Slave address
Pin description
Pin
1, 2
3
4
5
6
7
8
Rev. 01 — 19 January 2010
diagram”.
Description
not connected
active LOW protect reset input
ground supply voltage
serial data; open-drain I/O
serial clock; open-drain input
active HIGH write protect input
supply voltage
2
1
C-bus protocol that is usually matched to A2 (pin 3) on a
1024 × 8-bit CMOS EEPROM with access protection
0
fixed
1
0
1
selectable
B2
sofware
002aae789
B1 R/W
Figure
Figure
4.
PCA24S08A
5. Upon receipt of the
© NXP B.V. 2010. All rights reserved.
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