uda1351h NXP Semiconductors, uda1351h Datasheet - Page 11

• Manufacturer Part Number: uda1351h
• Description: 96 Khz Iec 958 Audio Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.4
By default the outputs of the digital data output interface
and the DAC will be muted until the IC is locked,
regardless the level on pin MUTE (in static mode) or the
state of bit MT of the sound feature register (in L3 mode).
In this way only valid data will be passed to the outputs.
This mute is done in the SPDIF interface and is a hard
mute, not a cosine roll-off mute.
If needed, this muting can be bypassed by setting
bit AutoMT to logic 0 via the L3 interface. As a result the IC
will no longer mute during out-of-lock situations.
8.5
The UDA1351H data path consists of the slicer and the
IEC 958 decoder, the digital data output and input
interfaces, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.
8.5.1
The UDA1351H IEC 958 decoder can select 1 out of 2
IEC 958 input channels. An on-chip amplifier with
hysteresis amplifies the IEC 958 input signal to CMOS
level (see Fig.5).
All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.
The extracted key parameters are:
2000 Jul 27
handbook, halfpage
Pre-emphasis
Audio sample frequency
Two-channel PCM indicator
Clock accuracy.
96 kHz IEC 958 audio DAC
Fig.5 IEC 958 input circuit and typical application.
75
Auto mute
Data path
IEC 958
10 nF
180 pF
INPUT
SPDIF0,
SPDIF1
15,
16
UDA1351H
MGL975
11
Both the lock indicator and the key channel status bits are
accessible via the L3 interface.
The UDA1351H supports the following sample
frequencies and data bit rates:
The UDA1351H supports timing level I, II and III as
specified by the IEC 958 standard.
8.5.2
In order to prevent noise at the FSDAC output when
switching between the SPDIF inputs, the following
procedures are recommended. This procedure uses an
external analog mute circuit as shown in Fig.3.
At switching between the two SPDIF inputs, the
switching inside the UDA1351H is done instantly. It may
occur that SPDIF words inside the SPDIF decoder of the
UDA1351H get corrupted. When no action is taken,
corrupted data can reach the FSDAC output.
f
f
f
f
f
f
Static mode:
– Activate the external analog mute circuit
– Select the proper SPDIF input signal
– Activate pin RESET to reset the PLL settings and the
– De-activate the external analog mute circuit.
L3 mode:
– Activate the external analog mute circuit
– Select the proper SPDIF input signal via the
– Toggle bit RST_PLL of the L3 interface to reset the
– De-activate the external analog mute circuit.
s
s
s
s
s
s
= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s
= 64.0 kHz, resulting in a data rate of 4.096 Mbits/s
= 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s
= 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.
PLL will synchronize again to the new input signal
L3 interface
PLL and the PLL will synchronize again to the new
input signal
SPDIF
SELECTION PROCEDURE
WARNING
Product specification
UDA1351H