uda1351h NXP Semiconductors, uda1351h Datasheet - Page 16

• Manufacturer Part Number: uda1351h
• Description: 96 Khz Iec 958 Audio Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.7
8.7.1
The UDA1351H has an L3 microcontroller interface and all
the digital sound processing features and various system
settings can be controlled by a microcontroller.
The controllable settings are:
The readable settings are:
The exchange of data and control information between the
microcontroller and the UDA1351H is LSB first and is
accomplished through a serial hardware L3 interface
comprising the following pins:
The exchange of bytes via the L3 interface is LSB first.
The L3 format has 2 modes of operation:
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.7).
The data transfer mode is characterized by L3MODE
being HIGH and is used to transfer one or more bytes
representing a register address, instruction or data.
2000 Jul 27
Restoring L3 defaults
Power-on
Selection of input channel, clock source, DAC input and
external input format
Selection of filter mode and settings of treble and bass
boost
Volume settings
Selection of soft mute via cosine roll-off (only effective in
L3 control mode) and bypass of auto mute
Selection of de-emphasis.
Mute status of interpolator
PLL locked
SPDIF input signal locked
Audio Sample Frequency (ASF)
Valid PCM data detected
Pre-emphasis of the IEC 958 input signal
ACcuracy of the Clock (ACC).
L3DATA: data line
L3MODE: mode line
L3CLK: clock line.
Address mode
Data transfer mode.
96 kHz IEC 958 audio DAC
L3 interface
G
ENERAL
16
Basically 2 types of data transfers can be defined:
Remark: when the device is powered up, at least one
L3CLOCK pulse must be given to the L3 interface to
wake-up the interface before starting sending to the device
(see Fig.7). This is only needed once after the device is
powered up.
8.7.2
The device address consists of 1 byte with:
Table 5 Selection of data transfer
8.7.3
After sending the device address, including Data
Operating Mode (DOM) bits indicating whether the
information is to be read or written, 1 data byte is sent
using bit 0 to indicate whether the information will be read
or written and bits 1 to 7 for the destination register
address.
Basically there are 3 methods for register addressing:
1. Addressing for write data: bit 0 is logic 0 indicating
2. Addressing for prepare read: bit 0 is logic 1 indicating
3. Addressing for data read action: in this case the device
Write action: data transfer to the device
Read action: data transfer from the device.
Bits 0 and 1 (called DOM bits) representing the type of
data transfer (see Table 5)
Bits 2 to 7 (address bits) representing a 6-bit device
address.
a write action to the destination register, followed by
bits 1 to 7 indicating the register address (see Fig.7)
that data will be read from the register (see Fig.8)
returns a register address prior to sending data from
that register. When bit 0 is logic 0, the register address
is valid; in case bit 0 is logic 1 the register address is
invalid.
BIT 0
0
1
0
1
D
R
EVICE ADDRESSING
EGISTER ADDRESSING
DOM
BIT 1
0
0
1
1
not used
not used
write data or prepare read
read data
Product specification
TRANSFER
UDA1351H