dsp56001a Freescale Semiconductor, Inc, dsp56001a Datasheet
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dsp56001a Summary of contents
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... ROMs containing sine, A-law, and -law tables. The DSP56001A contains a Serial Communication Interface (SCI), a Synchronous Serial Interface (SSI), and a parallel Host Interface (HI). This combination of features, illustrated in Figure 1 , makes the DSP56001A a cost-effective, high-performance solution for high-precision general purpose digital signal processing. The DSP56001A is intended as a replacement for the DSP56001 ...
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... Freescale Semiconductor, Inc. SECTION 1 SIGNAL/PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS (INCLUDES NOTES FOR DSP56001 TO DSP56001A DESIGN CONVERSION 4-1 SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 SECTION A ROM TABLE LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low ...
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... Two 256 24-bit on-chip data ROMs containing sine, A-law and -law tables • External memory expansion with 16-bit address and 24-bit data buses • Bootstrap loading from external data bus or Host Interface MOTOROLA For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com DSP56001A DSP56001A Features iii ...
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... Ceramic Quad Flat Pack (CQFP) surface-mount package • power supply PRODUCT DOCUMENTATION The three documents listed in Table 1 are required for a complete description of the DSP56001A and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): • ...
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... DSP, memory, peripherals, and instruction set DSP56001A Pin and package descriptions, and electrical and timing Data Sheet specifications Related Documentation Table 2 lists additional documentation relevant to the DSP56001A. Table 2 DSP56001A Related Documentation Document Name Digital Sine-Wave Synthesis Digital Stereo 10-band Graphic Equalizer ...
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... Freescale Semiconductor, Inc. DSP56001A Product Documentation Table 2 DSP56001A Related Documentation (Continued) Document Name Twin CODEC Expansion Board for the DSP56000 ADS Conference Bridging in the Digital Telecommunications Environment Implementation of Adaptive Controllers Calculating Timing Requirements of External SRAM Low Cost Controller for DSP56001 G.722 Audio Processing ...
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... Freescale Semiconductor, Inc. SIGNAL/PIN DESCRIPTIONS INTRODUCTION DSP56001A signals are organized into twelve functional groups as summarized in Table 1-1. Table 1-1 Signal Functional Group Allocations Functional Group Power (V ) CCX Ground (GND ) X Clock Address Bus Data Bus Bus Control Interrupt and Mode Control Host Interface (HI) Port ...
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... RXD Communications TXD Interface (SCI) RCLK 2 Port SSI Port 3 SC0–SC2 Synchronous SCK Serial Interface 2 SRD (SSI) Port STD DSP56001A/D, Rev to: www.freescale.com Interrupt mode IRQA IRQB Port B GPIO PB0–PB7 PB8–PB10 PB11 PB12 PB13 PB14 Port C GPIO PC0 PC1 ...
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... Data Bus Ground—These lines connect system ground to the data bus. D GND (1) Host Interface Ground—These lines supply ground connections for the Host Interface logic. MOTOROLA For More Information On This Product, Table 1-2 Power Connections Description lines and the GND CCQ Table 1-3 Ground Connections Description DSP56001A/D, Rev to: www.freescale.com DSP56001A Power lines. Q 1-3 ...
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... A0–A15 are tri-stated when the bus grant signal is asserted. Table 1-6 Data Bus Signals Signal Description Data Bus—These signals provide the bidirectional data bus for external program and data memory accesses. D0–D23 are tri-stated when the BG or RESET signal is asserted. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... DMA controller to become master of the external data bus D0–D23 and external address bus a0–a15. When operating mode register (OMR) bit 7 is clear and BR is asserted, the DSP56001A will always release the external data bus D0–D23, address bus A0–A15, and bus control signals PS, DS, X/Y, RD, and WR (i ...
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... When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET signal is deasserted, the initial chip operating mode is latched from MODA and MODB. The internal reset signal is deasserted synchronously with the internal clocks. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. DO NOT APPLY 10 VOLTS TO ANY PIN OF THE Subjecting any pin of the DSP56001A to voltages in excess of the specified TTL/CMOS levels will permanently damage the device. MOTOROLA For More Information On This Product, CAUTION DSP56001A (including DSP56001A/D, Rev to: www.freescale.com DSP56001A Interrupt and Mode Control ...
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... The signals are inputs unless HR/W is high and HEN is asserted, in which case H0–H7 become outputs, allowing the host processor to read the DSP56001A data. H0–H7 become outputs when HACK is asserted during HREQ assertion. Port B GPIO 0–7 (PB0–PB7)—These signals are GPIO signals (PB0– ...
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... For More Information On This Product, Signal Description When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56001A data. When HEN is asserted and HR/W is low, H0–H7 become inputs. Host data is latched in the DSP on the rising edge of HEN. Normally, a chip select signal derived from host address decoding and an enable strobe are used to generate HEN ...
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... Synchronous mode. The direction and function of the signal is defined by the RCM bit in the SCI Clock Control Register (SCCR). Port C GPIO 2 (PC2)—This signal is a GPIO signal called PC2 when the SCI TCLK function is not being used. After reset, the default state is GPIO input. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... After reset, the default state is GPIO input. serial bit rate clock for the SSI when only one clock is being used. Port C GPIO 6 (PC6)—This signal is GPIO signal PC6 when the SSI function is not being used. After reset, the default state is GPIO input. DSP56001A/D, Rev to: www.freescale.com DSP56001A 1-11 ...
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... After reset, the default state is GPIO input. from the SSI Transmitter Shift Register. Port C GPIO 8 (PC8)—This signal is GPIO signal PC8 when the SSI STD function is not being used. After reset, the default state is GPIO input. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. SPECIFICATIONS GENERAL CHARACTERISTICS The DSP56001A is fabricated in high-density HCMOS with TTL compatible inputs and outputs. Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Supply Voltage All Input Voltages Current Drain per Pin excluding V Storage Temperature Note: This device contains circuitry protecting against damage due to high static voltage or electrical fields ...
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... Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature. 2-2 For More Information On This Product, Symbol 13.0 (PQFP) DSP56001A/D, Rev to: www.freescale.com Value Rating 40 (CQFP) C/W 47 (PQFP) 7.0 (CQFP) C/W MOTOROLA ...
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... Min V CC 4.75 VIHC VIHR VIHM VIH V –0.5 ILC V –0.5 ILM V –0 –10 TSI CCI I CCW I CCS C IN DSP56001A/D, Rev to: www.freescale.com DSP56001A DC Electrical Characteristics Typ Max Units 4.5 5.0 5.5 V 5.0 5.25 V 4.0 — 2.5 — 3.5 — 2.0 — — ...
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... DC electrical characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56001A output levels are measured with the production test machine V respectively ...
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... Freescale Semiconductor, Inc. EXTERNAL CLOCK (EXTAL PIN) The DSP56001A system clock may be derived from the on-chip crystal oscillator as shown in Figure 2- may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected to the board or socket. The rise and fall times of this external clock should maximum. ...
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... IHC ILC Table 2-7 Clock Operation 27 MHz Symbol Min Max 150 150 250 500 CYC DSP56001A/D, Rev to: www.freescale.com V ILC Midpoint V IHC AA0360 33 MHz Unit Min Max 4 33 MHz 13.5 150 ns 13.5 150 ns 30 250 ns 60 500 ns MOTOROLA ...
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... T — — — 0 — 17 — 10 — DSP56001A/D, Rev to: www.freescale.com DSP56001A 33 MHz Unit Min Max — 75000 T — — ...
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... WS) – — WS) – — – — WS) – DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max + T — — — — WS) – — ...
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... — 65548 T — — 65534 T + — 65534 — DSP56001A/D, Rev to: www.freescale.com DSP56001A 33 MHz Unit Min Max — T – — – ...
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... Min Max Min 65548 T — 65548 — and T will not be constant. Since this stabilization period typically allowed to assure that the oscillator is stable before C DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max — — MOTOROLA ...
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... RESET MODA, MODB Figure 2-6 Operating Mode Select Timing MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing 10 Figure 2-4 Reset Timing IHM V ILM DSP56001A/D, Rev to: www.freescale.com DSP56001A V IHR 11 First Fetch AA0356 AA0887 V IHR IRQA, IRQB ...
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... General Purpose I/O 18 IRQA, IRQB Figure 2-7 External Level-Sensitive Fast Interrupt Timing IRQA, IRQB IRQA, IRQB Figure 2-8 External Interrupt Timing (Negative Edge-Triggered) 2-12 For More Information On This Product, First Interrupt Instruction Execution/Fetch General Purpose I/O 16 16A DSP56001A/D, Rev to: www.freescale.com AA0889 AA0890 MOTOROLA ...
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... Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing T0 DSP56001A/D, Rev to: www.freescale.com DSP56001A 24 AA0891 First Instruction Fetch AA0363 First IRQA Interrupt Instruction Fetch AA0364 ...
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... C 39 — 19 — 19 — — — — 4 — 0 — — 39 — — DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max — — — — — — ...
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... T + — t HSDL — t HSDL the time period required for the DSP56001 to sample any HSDL DSP56001A/D, Rev to: www.freescale.com DSP56001A Host I/O (HI) Timing 33 MHz Unit Min Max 0 — — — — — — ...
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... H0–H7 Data (Output) Valid Figure 2-13 Host Read Cycle (Non-DMA Mode) 2-16 For More Information On This Product Data Valid 49 RXM Read 32 44 Address Valid 42 38 Data Valid DSP56001A/D, Rev to: www.freescale.com 37 AA0223 47 RXL Read Address Valid Data Valid AA0224 MOTOROLA ...
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... Address Valid 40 34 Data Valid 32 46 RXM Read 37 38 Data Valid 32 46 TXM Write 34 Data Valid DSP56001A/D, Rev to: www.freescale.com DSP56001A Host I/O (HI) Timing 48 TXL Write Address Valid Data Valid AA0225 46 46 RXL Read Data Valid AA0230 46 46 TXL Write Data ...
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... — — – — — — 31 — DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Min Max 8 T — – 13 — – 13 — — — — – — – ...
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... Min Max 64 T — – 15 — – 15 — C — — – 77 — – 77 — C DSP56001A/D, Rev to: www.freescale.com DSP56001A — 1X Clock 33 MHz Unit Min Max 64 T — – 13 — – 13 — — ...
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... In the Wired-OR mode, TXD can be pulled Figure 2-18 SCI Asynchronous Mode Timing 2-20 For More Information On This Product Data Valid 61 62 Data Valid a) Internal Clock Data Valid 65 66 Data Valid b) External Clock Data Valid DSP56001A/D, Rev to: www.freescale.com AA0892 AA0893 MOTOROLA ...
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... DSP56001A/D, Rev to: www.freescale.com DSP56001A 33 MHz Case Unit Max — — – 13 — — ns – 13 — — xck ...
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... — DSP56001A/D, Rev to: www.freescale.com Case Unit Max — — — — — — — — ...
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... SSI control register. cyc DSP56001A/D, Rev to: www.freescale.com DSP56001A 33 MHz Case Unit Max — — — — — ...
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... In the Normal mode, the output flag state is asserted for the entire frame period. Figure 2-19 SSI Transmitter Timing 2-24 For More Information On This Product 100 100 99 First Bit 105 103 104 105 106 DSP56001A/D, Rev to: www.freescale.com 98 101A 101 Last Bit See Note AA0894 MOTOROLA ...
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... In the Normal mode, the output flag state is asserted for the entire frame period. Figure 2-20 SSI Receiver Timing MOTOROLA For More Information On This Product, Synchronous Serial Interface (SSI) Timing First Bit Last Bit DSP56001A/D, Rev to: www.freescale.com DSP56001A 87 See Note AA0895 2-25 ...
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... Number of Wait States, as determined by BCR ( 15) Capacitance Derating: The DSP56001A external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates linearly per additional capacitance from 250 pF of loading ...
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... — — — — ( ( — L DSP56001A/D, Rev to: www.freescale.com DSP56001A 33 MHz Unit Min Max 5 5 — — ...
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... — — — — DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max 0 — 5.5 — ns — — ( — 5 — ...
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... Figure 2-22 External Bus Asynchronous Timing MOTOROLA For More Information On This Product, External Bus Asynchronous Timing 115 116 117 118 127 131 129 122 121 133 132 130 125 124 Data Out DSP56001A/D, Rev to: www.freescale.com DSP56001A 119 AA0896 126 134 136 128 Data In AA0393 2-29 ...
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... TTL loads J L Capacitance Derating: The DSP56001A external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0–A15, D0–D23, PS, DS, RD, WR, X/Y) derates linearly per additional capacitance from 250 pF of loading. Port B and C pins (HI, SCI, SSI) derate linearly per additional capacitance from 250 pF of loading ...
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... MOTOROLA For More Information On This Product, External Bus Synchronous Timing 27 MHz Min Max the corresponding signal(s 143 142 147 Data Out 146 DSP56001A/D, Rev to: www.freescale.com DSP56001A 33 MHz Unit Min Max 144 149 148 Data In AA0395 2-31 ...
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... – ( ( — DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Min Max 2 2.5 — – — 6 – ...
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... However, BS will deassert before asserting again for the write cycle. Figure 2-24 Asynchronous Timings MOTOROLA For More Information On This Product, 27 MHz Min Max 12 — 158 123 125 Data Out DSP56001A/D, Rev to: www.freescale.com DSP56001A Bus Strobe / Wait Timing 33 MHz Unit Min Max 10 — ns 160 159 ...
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... During Read-Modify-Write Instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. Figure 2-25 Synchronous Timings 2-34 For More Information On This Product 152 153 147 145 Data Out DSP56001A/D, Rev to: www.freescale.com 149 154 144 148 Data In 142 146 AA0397 MOTOROLA ...
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... Diagrams of the pinouts of each package are included, and tables describing the pins allocated to each of the signals described in Table 3-1 through Table 3-5. The DSP56001A is available in 3 packages: • 132-pin plastic quad flat pack (PQFP), type ‘FC’ • 132-pin ceramic quad flat pack (CQFP), type ‘FE’ ...
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... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-1 Top View of the 132-pin Plastic (FC) Quad Flat Package 3-2 For More Information On This Product, (Top View) DSP56001A/D, Rev to: www.freescale.com nc D20 D19 D18 ...
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... To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-2 Bottom View of the 132-pin Plastic (FC) Quad Flat Package MOTOROLA For More Information On This Product, Orientation Mark (chamfered edge on Top side) (Bottom View) DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information 18 nc H3/PB3 H2/PB2 ...
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... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-3 Top View of the 132-pin Ceramic (FE) Quad Flat Package 3-4 For More Information On This Product, Orientation Mark (Top View) DSP56001A/D, Rev to: www.freescale.com nc D20 D19 D18 GNDD ...
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... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-4 Bottom View of the 132-pin Ceramic (FE) Quad Flat Package MOTOROLA For More Information On This Product, (Bottom View) DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information 18 nc ...
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... XTAL HA2 HA1 HACK MODA/ EXTAL GNDQ HA0 IRQA VCCQ VCCH (Top View) GNDN VCCN GNDN A11 A10 DSP56001A/D, Rev to: www.freescale.com HEN HR HREQ RXD GNDH TXD SC0 SCLK GNDQ VCCQ SCK ...
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... EXTAL MODA/ IRQA CCH C (Bottom View) GNDN V GNDN CCN A11 A10 DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information MODB/ D22 D21 D19 IRQB D20 D17 D23 D18 D15 GNDD D16 D14 D13 D12 ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information The DSP56001A signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-1. Table 3-1 DSP56001A General Purpose I/O Pin Identification Pin Number 132 pin “FC” PQFP “FE” CQFP ...
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... Freescale Semiconductor, Inc. Table 3-1 DSP56001A General Purpose I/O Pin Identification Pin Number 132 pin “FC” PQFP “FE” CQFP Table 3-2 DSP56001A Signal Identification by Pin Number Pin No. Signal Name A1 D19 A2 D21 A3 D22 A4 MODB/IRQB A5 RESET A6 XTAL A7 HA2/PB10 A8 HA1/PB9 A9 HACK/PB14 ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-2 DSP56001A Signal Identification by Pin Number Pin No. Signal Name A12 H6/PB6 A13 H5/PB5 B1 D17 B2 D20 B4 D23 B5 MODA/IRQA B6 EXTAL B7 GNDQ B8 HA0/PB8 B10 HREQ/PB13 B11 H7/PB7 B12 H4/PB4 B13 H3/PB3 C1 D15 C2 D18 C6 V CCQ C9 V CCH ...
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... Freescale Semiconductor, Inc. Table 3-3 DSP56001A Signal Identification by Pin Number Pin No. Signal Name 1 HA2/PB10 2 HA1/PB9 HA0/PB8 6 HACK/PB14 HEN/PB12 9 HR/W/PB11 10 HREQ/PB13 11 H7/PB7 12 V CCH 13 V CCH 14 H6/PB6 15 H5/PB5 16 H4/PB4 H3/PB3 20 H2/PB2 H1/PB1 23 GNDH 24 GNDH 25 H0/PB0 MOTOROLA For More Information On This Product, Pin No ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-3 DSP56001A Signal Identification by Pin Number Pin No. Signal Name 76 A12 77 A13 A14 80 A15 GNDD 91 GNDD Note: 1. “nc” are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias ...
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... Freescale Semiconductor, Inc. Table 3-4 DSP56001A Identification by Signal Name 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No A10 71 A11 75 A12 76 A13 77 A14 79 A15 ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-4 DSP56001A Identification by Signal Name (Continued) 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No GNDN 74 GNDQ 33 GNDQ 34 GNDQ 130 GNDQ 131 ...
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... Freescale Semiconductor, Inc. Table 3-4 DSP56001A Identification by Signal Name (Continued) 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No. IRQB 121 MODA 123 MODB 121 NMI none PB0 25 PB1 22 SC1 40 SC2 37 SCK 32 SCLK 29 SRD 42 STD 39 TXD 28 V 100 CCD V 101 ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-4 DSP56001A Identification by Signal Name (Continued) 132 pin Signal “FC” PQFP or Name “FE” CQFP Pin No X/Y 48 XTAL 126 Power and ground pins have special considerations for noise immunity. See the section Design Considerations ...
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... Freescale Semiconductor, Inc. Table 3-5 DSP56001A Power Supply Pins (Continued) 132 pin “FC” PQFP or “FE” CQFP Pin No. 100 101 90 91 111 112 35 36 128 129 33 34 130 131 MOTOROLA For More Information On This Product, 88 pin “RC” PGA Power Supply Pin No ...
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... DIMENSIONS AND DETERMINED AT DATUM PLANE DIMENSION F DOES NOT INCLUDE H DAMBAR PROTRUSIONS. DAMBAR GAGE PROTRUSION SHALL NOT CAUSE THE PLANE LEAD WIDTH TO EXCEED 0.019 DSP56001A/D, Rev to: www.freescale.com G 128X X= VIEW AB BASE METAL ( ...
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... L-N M VIEW AE NOTES: SEATING PLANE 1. 2. 0.004 (AB (R) (R) K (AA) DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information X= VIEW AC F PLATING Z BASE METAL D M 0.005 T L-N M SECTION AD 132 PLACES ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14 ...
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... 0.003 T A MATRIX M 0.010 X PINS Top View Figure 3-10 PGA Shipping Tray DSP56001A/D, Rev to: www.freescale.com NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. PIN DIAMETER DOES NOT INCLUDE SOLDER DIP OR CUSTOM FINISHES. G INCHES DIM MIN ...
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... Freescale Semiconductor, Inc. Orientation Marks Figure 3-11 PQFP Shipping Tray Orientation Marks Figure 3-12 CQFP Shipping Tray MOTOROLA For More Information On This Product, Top View Top View DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information 4 9 AA1132 AA0897 3-21 ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information 3-22 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... The DSP56001A die utilizes a faster technology than the DSP56001 result, many DSP56001A signals exhibit faster rise and fall times than the same signals on the DSP56001. These faster edges may generate more radiated noise and EMI, and may require more attention to these issues (e ...
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... On the DSP56001A this pipeline delay has been removed address register (Mn, Nn, or Rn) is directly changed with a MOVEP instruction, the updated contents will be available for use during the following instruction ...
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... Wake-up from the Stop and Wait operating modes with IRQA and IRQB is longer on the DSP56001A by one Tc period. SCI/SSI INITIALIZATION TIMING On the DSP56001A, the SCI and SSI clocks are stopped when the peripherals are not enabled in order to save power result, the initialization time of the SCI and SSI is longer on the DSP56001A than on the DSP56001. ...
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... Freescale Semiconductor, Inc. DSP56001A Substituting the DSP56001A for the DSP56001 CONTROL REGISTERS The OMR and the Status Register on the DSP56001A have been altered from those on the DSP56001. Refer to Table 4-2 for details of these alterations. Table 4-2 Summary of Control Register Differences DSP56001 REGISTER BIT ...
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... P can be neglected. An appropriate relationship between I/O + 273 273 (at equilibrium) for a known T D can be obtained by solving equations (1) and (2) iteratively DSP56001A/D, Rev to: www.freescale.com DSP56001A Heat Dissipation . Using A ) can be separated into two ). These terms are CA is user-dependent and CA so that CA 4-5 ...
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... This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. 4-6 For More Information On This Product, CAUTION ). CC power source to GND. CC and GND circuits. CC DSP56001A/D, Rev to: www.freescale.com pin on the DSP, CC and CC MOTOROLA ...
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... This is a common problem when two asynchronous systems are connected. The situation exists in the Host Interface. The following paragraphs present considerations for proper operation. MOTOROLA For More Information On This Product, –12 6 5.5 8. 227 mA – max), reflects the maximum possible switching of CCI DSP56001A/D, Rev to: www.freescale.com DSP56001A Power Consumption 4-7 ...
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... HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HREQ pin). 4-8 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... A very small probability exists that the DSP will read the status bits during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. MOTOROLA For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com DSP56001A Host Port Considerations 4-9 ...
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... The lowest cost DSP56001A-based system is shown in Figure 4-1. It uses no run time external memory and requires only two chips, the DSP56001A and a low cost EPROM. The EPROM read access time should be less than 780 nanoseconds when the DSP56001A is operating at a clock rate of 20.5 MHz. ...
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... Figure 4-2 Port A Bootstrap with External Data RAM—Mode 1 MOTOROLA For More Information On This Product, DSP56001A HACK DS X/Y A0–A10 11 PS MODB/ IRQB CE A0–A10 2716 MODA/ D0–D7 IRQA RESET 8 D0–D23 DSP56001A/D, Rev to: www.freescale.com DSP56001A Application Examples 10 A0–A9 A10 2018-55 (3) D0–D23 D23 AA0905 4-11 ...
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... Freescale Semiconductor, Inc. DSP56001A Application Examples Figure 4-3 shows the DSP56001A bootstrapping via the Host Port from an MC68000 IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. Figure 4-3 DSP56001A Host Bootstrap Example—Mode 5 ...
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... Freescale Semiconductor, Inc. In Figure 4-4, the DSP56001A is operated in Mode 3 with external program memory and the reset vector at location $0000. The programmer can overlay the high-speed on-chip Program RAM with DSP algorithms by using the MOVEM instruction IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. ...
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... IRQA, and IRQB must be driven to the logic levels appropriate for the application. 2. MODA and MODB must be driven to the logic levels appropriate for the application. Figure 4-5 Reset Circuit Using MC34064/MC33064 4-14 For More Information On This Product, on the DSP56001A is at least 4.5 V before initiating CC + (1) ...
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... Freescale Semiconductor, Inc. Figure 4-6 shows the DSP56001A connected to the bus of an IBM-PC computer. This circuit is complete and does not require external ROM or RAM to load and execute code from the PC. The PAL equations and other details of this circuit are available in the application report entitled “ ...
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... Freescale Semiconductor, Inc. DSP56001A Application Examples 4-16 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. ORDERING INFORMATION Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 5-1 DSP56001A Ordering Information Part Package Type DSP56001A Ceramic Pin-Grid Array (PGA) Plastic Quad Flat Pack (PQFP) ...
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... Freescale Semiconductor, Inc. DSP56001A 5-2 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... M_22 DC M_23 DC M_24 DC M_25 DC M_26 DC M_27 DC M_28 DC M_29 DC M_2A DC M_2B DC M_2C DC M_2D DC DSP56001A/D, Rev to: www.freescale.com ROM Table Listings $327C00 ; 3231 $307C00 ; 3103 $2E7C00 ; 2975 $2C7C00 ; 2847 $2A7C00 ; 2719 $287C00 ; 2591 $267C00 ; 2463 $247C00 ; 2335 $227C00 ; 2207 $207C00 ; 2079 $1EFC00 ; 1983 $1DFC00 ...
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... M_74 DC $005800 M_75 DC $005000 M_76 DC $004800 M_77 DC $004000 M_78 DC $003800 M_79 DC $003000 M_7A DC $002800 M_7B DC $002000 M_7C DC $001800 M_7D DC $001000 M_7E DC $000800 M_7F DC $000000 DSP56001A/D, Rev to: www.freescale.com ; 163 ; 155 ; 147 ; 139 ; 131 ; 123 ; 115 ; 107 ; ...
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... A_C6 DC A_C7 DC A_C8 DC A_C9 DC A_CA DC A_CB DC A_CC DC A_CD DC A_CE DC A_CF DC A_D0 DC A_D1 DC DSP56001A/D, Rev to: www.freescale.com ROM Table Listings $720000 ; 3648 $7E0000 ; 4032 $7A0000 ; 3904 $660000 ; 3264 $620000 ; 3136 $6E0000 ; 3520 $6A0000 ; 3392 $2B0000 ; 1376 $290000 ; 1312 $2F0000 ; 1504 $2D0000 ; 1440 $230000 ...
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... A_FA DC $03F000 ; 126 A-4 For More Information On This Product, 15 A_FB DC 13 A_FC DC 3 A_FD DC 1 A_FE DC 7 A_FF DSP56001A/D, Rev to: www.freescale.com $03D000 ; 122 $033000 ; 102 $031000 ; 98 $037000 ; 110 $035000 ; 106 MOTOROLA ...
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... S_2E DC $73B5EC S_2F DC $7504D3 S_30 DC $7641AF S_31 DC $776C4F S_32 DC $788484 S_33 DC $798A24 S_34 DC $7A7D05 S_35 DC $7B5D04 DSP56001A/D, Rev to: www.freescale.com ROM Table Listings Sine Wave Table ; +0.5956993103 ; +0.6152315736 ; +0.6343932748 ; +0.6531729102 ; +0.6715589762 ; +0.6895405054 ; +0.7071068287 ; +0.7242470980 ; +0.7409511805 ; +0.7572088242 ; +0.7730104923 ; +0.7883464098 ; +0.8032075167 ; +0.8175848722 ...
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... S_7F DC $03242B S_80 DC $000000 S_81 DC $FCDBD5 S_82 DC $F9B827 S_83 DC $F69570 S_84 DC $F3742D S_85 DC $F054D9 S_86 DC $ED37F0 S_87 DC $EA1DEC DSP56001A/D, Rev to: www.freescale.com ; +0.7242470980 ; +0.7071068287 ; +0.6895405054 ; +0.6715589762 ; +0.6531729102 ; +0.6343932748 ; +0.6152315736 ; +0.5956993103 ; +0.5758082271 ; +0.5555701852 ; +0.5349975824 ; +0.5141026974 ; +0.4928981960 ; +0.4713967144 ; +0.4496113062 ; +0.4275551140 ; +0.4052414000 ; +0.3826833963 ...
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... S_D2 DC $8C4A14 S_D3 DC $8DAAD3 S_D4 DC $8F1D34 S_D5 DC $90A0FD S_D6 DC $9235F3 S_D7 DC $93DBD7 S_D8 DC $959267 S_D9 DC $975961 DSP56001A/D, Rev to: www.freescale.com ROM Table Listings Sine Wave Table ; -0.9329928160 ; -0.9415441155 ; -0.9495282173 ; -0.9569402933 ; -0.9637761116 ; -0.9700313210 ; -0.9757022262 ; -0.9807853103 ; -0.9852777123 ; -0.9891765118 ; -0.9924796224 ; -0.9951847792 ; -0.9972904921 ; -0.9987955093 ...
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... S_F6 DC $E0E607 ; -0.2429800928 S_F7 DC $E3F47E ; -0.2191012055 S_F8 DC $E70748 ; -0.1950902939 S_F9 DC $EA1DEC ; -0.1709619015 S_FA DC $ED37F0 ; -0.1467303932 S_FB DC $F054D9 ; -0.1224106997 S_FC DC $F3742D ; -0.0980170965 S_FD DC $F69570 ; -0.0735644996 S_FE DC $F9B827 ; -0.0490676016 S_FF DC $FCDBD5 ; -0.0245412998 A-8 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Mfax is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...