dsp56001a Freescale Semiconductor, Inc, dsp56001a Datasheet - Page 48

• Manufacturer Part Number: dsp56001a
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

DSP56001A
External Bus Synchronous Timing
EXTERNAL BUS SYNCHRONOUS TIMING
V
T
Capacitance Derating: The DSP56001A external bus timing specifications are designed and
tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive
capability of the external bus pins (A0–A15, D0–D23, PS, DS, RD, WR, X/Y) derates linearly at 1
ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI,
SCI, SSI) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading.
Active-low lines should be pulled up in a manner consistent with the AC and DC specifications.
2-30
J
CC
= -40˚ to +105˚ C, C
Num
140
141
142
143
144
145
146
147
148
149
= 5.0 V 10% for 27 MHz, V
Clk Low transition to
Address Valid
Clk High transition to WR
Assertion(See Note 1, 2)
Clk High transition to WR
Deassertion
Clk High transition to RD
Assertion
Clk High transition to RD
Deassertion
Clk Low transition to Data-
Out Valid
Clk Low transition to Data-
Out Invalid (See Note 3)
Data-In Valid to Clk High
transition (Setup)
Clk High transition to
Data-In Invalid (Hold)
Clk Low transition to
Address Invalid (See Note 3)
•
•
Characteristics
WS=0
WS>0
L
= 50 pF + 1 TTL loads
Table 2-14 External Bus Synchronous Timing
Freescale Semiconductor, Inc.
For More Information On This Product,
CC
DSP56001A/D, Rev. 1
= 5.0 Vdc 5% for 33 MHz,
Go to: www.freescale.com
Min
—
—
12
0
0
5
0
3
4
4
2
27 MHz
T
H
Max
19
17
16
16
13
19
—
—
—
—
+ 17
Min
3.5
—
—
12
0
0
5
0
3
4
2
33 MHz
T
H
Max
10.5
19
17
13
16
19
—
—
—
—
+ 17
MOTOROLA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns