dsp56001a Freescale Semiconductor, Inc, dsp56001a Datasheet - Page 28

• Manufacturer Part Number: dsp56001a
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

DSP56001A
RESET, Stop, Mode Select, and Interrupt Timing
2-10
Note:
Num
28 Delay from Level-Sensitive
Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued)
IRQA Assertion to Fetch of First
Interrupt Instruction (when
exiting ‘Stop’)
(See Note 1)
1.
2.
3.
•
•
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
• after power-on reset, and
• when recovering from Stop mode.
During this stabilization period, T
varies, a delay of 75,000 T
executing programs.
While it is possible to set OMR Bit 6 = 1 when using the internal crystal oscillator, it is not
recommended and these specifications do not guaraantee timings for that case.
Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset, and
• when recovering from Stop mode.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19
through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the
deasserted Edge-Triggered mode is recommended when using fast interrupt. Long interrupts are
recommended when using Level-Sensitive mode.
Internal Crystal
Oscillator Clock, OMR
Bit 6 = 0
Stable External Clock,
OMR Bit 6 = 1
Characteristics
Freescale Semiconductor, Inc.
For More Information On This Product,
C
DSP56001A/D, Rev. 1
is typically allowed to assure that the oscillator is stable before
65548 T
Go to: www.freescale.com
20 T
C
Min
, T
H,
C
and T
27 MHz
C
L
will not be constant. Since this stabilization period
Max
—
—
65548 T
20 T
Min
C
33 MHz
C
Max
—
—
MOTOROLA
Unit
ns
ns