tspc860 ATMEL Corporation, tspc860 Datasheet
tspc860
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tspc860 Summary of contents
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... Two-wire Interface (TWI) compatible with protocols such Mod- erate to high digital signal processing (DSP) functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories (DRAMs) ...
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... Parallel I/O Baud Rate Generators Parallel Interface Port SCC1 SCC2 Time Slot Assigner TSPC860 [Preliminary] 2 The TSPC860 is functionally composed of three major blocks: • A 32-bit PowerPC Core with MMUs and Caches • A System Interface Unit • A Communications Processor Module I-Cache I-MMU ...
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... Main Features 2129B–HIREL–12/04 The Following is a List of the TSPC860’s Important Features: • Fully Static Design • Four Major Power Saving Modes • 357-pin Ball Grid Array Packaging (Plastic) • 32-bit Address and Data Busses • Flexible Memory Management • ...
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... TSPC860 [Preliminary] 4 • Four serial communications controllers – Protocols Supported by ROM or Downloadable Microcode and Include, but Limited to, the Digital Portion of: - Ethernet/IEEE 802.3 CS/CDMA - HDLC/SDLC and HDLC bus - Apple Talk - Signaling System #7 (RAM Microcode Only) - Universal Asynchronous Receiver Transmitter (UART) - Synchronous UART ...
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Pin Assignment Plastic Ball Grid Array Figure 2. Pin Assignment: Top View PD10 PD8 PD3 PD14 PD13 PD9 PD6 PA0 PB14 PD15 PD4 PA1 PC5 PC4 PD11 PC6 PA2 PB15 PD12 PA4 PB17 PA3 VDDL PB19 PA5 PB18 PB16 PA7 ...
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... Signal Description Figure 3. TSPC860 External Signals VDDSYN/VSSSYN/VSSSYN1/VDDH/VDDL/VSS/KAPWR TIN1/L1RCLKA/BRGO1/CLK1/PA[7] BRGCLK1/TOUT1/CLK2/PA[6] TIN2/L1TCLKA/BRGO2/CLK3/PA[5] BRGCLK2/L1RCLKB/TOUT3/CLK6/PA[2] L1TCLKB/TOUT4/CLK8/PA[0] SMTXD2/L1CLKOB/PB[21] SMRXD2/L1CLKOA/PB[20] L1ST1/RTS1/DREQ0/PC[15] L1ST2V/RTS2/DREQ1/PC[14] CTS3/SDACK2/L1TSYNCB/PC[7] CTS4/SDACK1/L1TSYNCA/PC[5] TSPC860 [Preliminary] 6 This section describes the signals on the TSPC860. 129 RXD1/PA[15] 1 TXD1/PA[14] 1 RXD2/PA[13] 1 TXD2/PA[12] 1 L1TXDB/PA[11] 1 L1RXDB/PA[10] 1 L1TXDA/PA[9] 1 L1RXDA/PA[ TOUT2/CLK4/PA[4] 1 TIN3/BRGO3/CLK5/PA[ TIN4/BRGO4/CLK7/PA[1] ...
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... Figure 4. TSPC860 Signals and Pin Numbers (Part 1) 2129B–HIREL–12/04 7 ...
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... Figure 5. TSPC860 Signals and Pin Numbers (Part 2) TSPC860 [Preliminary] 8 2129B–HIREL–12/04 ...
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... TS Hi-Z 2129B–HIREL–12/04 The TSPC860 system bus consists of all signals that interface with the external bus. Many of these signals perform different functions, depending on how the user assigns them. The following input and output signals are identified by their abbreviation. Each signal’s pin number can be found in Figure 4 and Figure 5. ...
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... D1 Open-drain Transfer Error Acknowledge—Indicates that a bus error occurred in the current transaction. The TSPC860 asserts TEA when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. Asserting TEA terminates the bus cycle, thus ignoring the state of TA. TEA requires the use of an external pull-up resistor ...
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... G4 Bidirectional Bus Request—Asserted low when a possible master is requesting ownership of the bus. When the TSPC860 is configured to work with the internal arbiter, this signal is configured as an input. When the TSPC860 is configured to work with an external arbiter, this signal is configured as an output and asserted every time a new transaction is intended to be initiated (no parking on the bus) ...
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... Bidirectional Bus Grant—Asserted low when the arbiter of the external bus grants the bus to a specific device. When the TSPC860 is configured to work with the internal arbiter configured as an output and asserted every time the external master asserts BR and its priority request is higher than any internal sources requiring a bus transfer ...
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... Description C7 Output Write Enable 0—Output asserted when a write access to an external slave controlled by the GPCM is initiated by the TSPC860 asserted if D(0-7) contains valid data to be stored by the slave device. Byte Select 0 on UPMB—Output asserted under control of the UPMB, as programmed by the user read or write transfer, the line is only asserted if D(0-7) contains valid data. IO Device Read— ...
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... Reset Configuration—The TSPC860 samples this input while HRESET is asserted. If RSTCONF is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. When RSTCONF is negated, the TSPC860 uses the default configuration mode. Note that the initial base address of internal registers is determined in this sequence. ...
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... Input Port A 0-1—The TSPC860 monitors these inputs that are reflected in the PIPR and PSCR of the PCMCIA interface. U3 Input Input Port A 2—The TSPC860 monitors these inputs; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. I/O Device A is 16-Bits Ports Size—The TSPC860 monitors this input when a transaction under the control of the PCMCIA interface is initiated to an I/O region in socket A of the PCMCIA space ...
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... This signal is not used for transactions initiated by external masters. G1 Bidirectional Input Port B 3 — The TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Instruction Watchpoint 2—This output reports the detection of an instruction watchpoint in the program flow executed by the core. Visible Instruction Queue Flush Status— ...
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... Output Port 0-1—The TSPC860 generates these outputs as a result of a write to the PGCRA register in the PCMCIA interface. L1 Bidirectional Output Port 2—This output is generated by the TSPC860 as a result of a write to the PGCRB register in the PCMCIA interface. Mode Clock 1—Input sampled when PORESET is negated to configure PLL/clock mode. ...
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... Output Burst Address—Outputs that duplicate A(28-29) values when one of M2 the following occurs: An internal master in the TSPC860 initiates a transaction on the external bus An asynchronous external master initiates a transaction A synchronous external master initiates a single beat transaction The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer ...
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Table 1. Signal Descriptions (Continued) Name Reset Number PA[9] L1TXDA PA[8] L1RXDA PA[7] CLK1 TIN1 L1RCLKA BRGO1 PA[6] CLK2 TOUT1 BRGCLK1 PA[5] CLK3 TIN2 L1TCLKA BRGO2 PA[4] Hi-Z CLK4 TOUT2 PA[3] CLK5 TIN3 BRGO3 PA[2] CLK6 TOUT3 L1RCLKB BRGCLK2 2129B–HIREL–12/04 ...
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... D19 Bidirectional General-Purpose I/O Port B Bit 28—Bit 29 of the general-purpose (Optional: I/O port B. Open-drain) SPIMISO—SPI input data when the TSPC860 is a master; SPI output data when slave. BRGO4—BRG4 output clock. E19 Bidirectional General-Purpose I/O Port B Bit 27—Bit 27 of the general-purpose (Optional: I/O port B ...
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Table 1. Signal Descriptions (Continued) Name Reset Number PB[23] SMSYN1 SDACK1 PB[22] SMSYN2 SDACK2 PB[21] SMTXD2 L1CLKOB PB[20] SMRXD2 L1CLKOA PB[19] RTS1 L1ST1 PB[18] RTS2 L1ST2 PB[17] Hi-Z L1RQB L1ST3 PB[16] L1RQA L1ST4 PB[15] BRGO3 2129B–HIREL–12/04 Type Description K17 Bidirectional ...
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... L1ST4 PC[11] CTS1 PC[10] Hi-Z CD1 TGATE1 PC[9] CTS2 PC[8] CD2 TGATE2 TSPC860 [Preliminary] 22 Type Description U18 Bidirectional General-Purpose I/O Port B Bit 14—Bit 14 of the general-purpose I/O port B. RSTRT1—SCC1 serial CAM interface outputs that marks the start of a frame. D16 Bidirectional General-Purpose I/O Port C Bit 15—Bit 15 of the general-purpose I/O port C. DREQ0— ...
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Table 1. Signal Descriptions (Continued) Name Reset Number PC[7] CTS3 L1TSYNCB SDACK2 PC[6] CD3 L1RSYNCB PC[5] CTS4 L1TSYNCA SDACK1 PC[4] CD4 L1RSYNCA PD[15] L1TSYNCA PD[14] L1RSYNCA PD[13] L1TSYNCB PD[12] Hi-Z L1RSYNCB PD[11] RXD3 PD[10] TXD3 PD[9] RXD4 PD[8] TXD4 2129B–HIREL–12/04 ...
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... A.3) TDO Low DSDO TRST Pulled up SPARE[1-4] Hi-Z B7, H18, V15, H4 Power Supply Figure 4 TSPC860 [Preliminary] 24 Type Description T15 Bidirectional General-Purpose I/O Port D Bit 7—Bit 7 of the general-purpose I/O port D. RTS3—Active low request to send output indicates that SCC3 is ready to transmit data. V16 Bidirectional General-Purpose I/O Port D Bit 6—Bit 6 of the general-purpose I/O port D. RTS4— ...
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... TSPC860, to the system both. Figure 6 compares three-state buffers and active pull-up buffers graphically in general terms ...
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... External logic can drive TA at any point before this, thus terminating the cycle early. [For example, assume the GPCM is programmed to drive TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then the TA will be accepted by the TSPC860 as a cycle termination.] For chip-selects controlled by the UPM, the TA buffer is enabled as an output throughout the entire bus cycle ...
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... For TSPC860 rev B and later, TDI/DSDI should be pulled oscillating when unused. • For TSPC860 rev A.3 and earlier, TCK/DSCK should be connected to ground configured for its DSCK function, as stated above. However, for these versions of the TSPC860, the pull-down resistor must be strong (for example overcome the internal pull-up resistor ...
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... IP_B[0-1]/IWP[0-1]/VFLS[0-1] IP_B3/IWP2/VF2 IP_B4/LWP0/VF0 IP_B5/LWP1/VF1 This specifications describes the specific requirements for the microcontroller TSPC860, in compliance with MIL-STD-883 class Q or Atmel standard screening. 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535 appendix A: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein ...
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... Package Absolute Maximum Ratings Absolute Maximum Rating for the TSPC860 Parameter I/O Supply Voltage Internal Supply Voltage Backup Supply Voltage PLL Supply Voltage Input Voltage Storage Temperature Range Table 4. Thermal Characteristics Rating Natural Convection (1) Junction to Ambient Air Flow (200 ft/min) (4) Junction to Board ...
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... Input Leakage Current 3.6V (Except TMS, TRST, DSCK and DSDI pins) IN Input Leakage Current (Except TMS, TRST, DSCK and DSDI pins) IN Output High Voltage -2.0 mA Except XTAL, XFC, and Open drain pins TSPC860 [Preliminary] 30 (3) Table 5. Power Dissipation ( Die Revision Frequency D.4 50 ...
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Table 6. DC Electrical Specification with V Characteristic Output Low Voltage IOL = 2.0 mA CLKOUT A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, ...
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... A. Maxi mu m Output Delay Speci ficat ion B. Minim um Out put Hold Tim e The timing for the TSPC860 bus shown assumes load for maximum delays and load for minimum delays. For loads other than 50 pF, maximum delays can be derated per 10 pF. ...
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Table 7. Bus Operation Timings Num Characteristic B1 CLKOUT Period B1a EXTCLK to CLKOUT Phase Skew (EXTCLK > 15 MHz and MF B1b EXTCLK to CLKOUT Phase Skew (EXTCLK > 10 MHz and MF < 10) B1c CLKOUT Phase Jitter ...
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... ACS = 11, TRLX = 0 B25 CLKOUT Rising Edge to OE, WE(0:3) asserted B26 CLKOUT Rising Edge to OE negated B27 A(0:31) and BADDR(28:30 asserted -GPCM- ACS = 10, TRLX = 1 B27a A(0:31) and BADDR(28:30 asserted -GPCM- ACS = 11, TRLX = 1 TSPC860 [Preliminary MHz 40 MHz Min Max Min Max 2. ...
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Table 7. Bus Operation Timings (Continued) Num Characteristic B28 CLKOUT rising edge to WE(0:3) negated GPCM write access CSNT = 0 B28a CLKOUT falling Edge to WE(0:3) negated -GPCM- write access TRLX = 0, CSNT = 1, EBDF = 0 ...
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... B32 CLKOUT Falling Edge to BS valid - as requested by control bit BST4 in the corresponding word in the UPM B32a CLKOUT Falling Edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 TSPC860 [Preliminary MHz 40 MHz Min Max Min Max Min 13.15 – ...
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Table 7. Bus Operation Timings (Continued) Num Characteristic B32b CLKOUT Rising Edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM B32c CLKOUT Rising Edge to BS valid - as requested by ...
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... The timing for BR output is relevant when the PC860 is selected to work with the external bus arbiter. The timing for BG out- put is relevant when the PC860 is selected to work with internal bus arbiter. 5. The timing required for BR input is relevant when the TSPC860 is selected to work with internal bus arbiter. The timing for BG input is relevant when the TSPC860 is selected to work with internal bus arbiter. ...
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Figure 9. Synchronous Output Signals Timing CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 10. Synchronous Active Pull-up and Open Drain Output Signals Timing CLKOUT TS, BB TA, BI TEA 2129B–HIREL–12/ B8a B9 B8b B11 ...
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... CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 12. Input Data Timing in Normal Case CLKOUT TA D[0:31], DP[0:3] Figure 13. Input Data Timing when controlled by UPM in the Memory Controller CLKOUT TA D[0:31], DP[0:3] TSPC860 [Preliminary] 40 B16 B17 B16a B17a B16b B17 B16 B17 B18 B19 B20 B21 2129B–HIREL–12/04 ...
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Figure 14. External Bus Read Timing (GPCM Controlled – ACS = ‘00’) CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] 2129B–HIREL–12/04 B11 B12 B8 B22 B25 B28 B18 B23 B26 B19 41 ...
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... Figure 15. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 16. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] TSPC860 [Preliminary] 42 B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b B22c B24a B25 ...
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Figure 17. External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’) CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] 2129B–HIREL–12/04 B12 B8 B22a B27 B27a B22b B22c B18 B23 B26 B19 43 ...
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... Figure 18. External Bus Write Timing (GPCM controlled – TRLX = ‘0’, CSNT = ‘0’) CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] TSPC860 [Preliminary] 44 B11 B12 B8 B22 B25 B26 B8 B30 B23 B28 B29b B29 B9 2129B–HIREL–12/04 ...
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Figure 19. External Bus Write Timing (GPCM controlled – TRLX = ‘0’, CSNT = ‘1’) CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] 2129B–HIREL–12/04 B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g ...
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... Figure 20. External Bus Write Timing (GPCM controlled – TRLX = ‘1’, CSNT = ‘1’) CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] TSPC860 [Preliminary] 46 B12 B8 B22 B28b B28d B25 B26 B8 B28a B28c B30b B30d B23 B29e B29i B29d B29h B29b B9 2129B–HIREL–12/04 ...
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Figure 21. External Bus Timing (UPM Controlled Signals) CLKOUT A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 22. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing CLKOUT UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] 2129B–HIREL–12/04 B8 B31a B31d B31 B34 B34a ...
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... Figure 23. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing CLKOUT UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 24. Synchronous External Master Access Timing – GPCM handled ACS = ‘00’ CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx TSPC860 [Preliminary] 48 B37 B38 B41 B42 B40 B22 2129B–HIREL–12/04 ...
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... The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLK- OUT. The timings I41, I42 and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the TSPC860 is able to support. 2129B–HIREL–12/04 B39 ...
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... WAITA and WAITB valid to CLKOUT rising (1) edge P56 CLKOUT rising edge to WAITA and WAITB (1) invalid Notes: 1. PSST = 1. Otherwise add PSST times cycle time. 2. PSHT = 1. Otherwise add PSHT times cycle time. TSPC860 [Preliminary] 50 I39 I40 I41 I43 I43 33 MHz 40 MHz Min Max Min 20 ...
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These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only detected 2 cycles before the PSL timer expiration. Figure 29. ...
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... Table 10. PCMCIA Port Timing Num Characteristic P57 CLKOUT to OPx Valid P58 HRESET negated to OPx drive P59 IP_Xx valid to CLKOUT Rising Edge P60 CLKOUT Rising Edge to IP_Xx invalid Note: 1. OP2 and OP3 only. TSPC860 [Preliminary] 52 P44 P46 P45 P48 P50 P52 P53 B8 P55 P56 33 MHz ...
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Figure 32. PCMCIA Output Port Timing CLKOUT Output Signals HRESET OP2, OP3 Figure 33. PCMCIA Input Port Timing CLKOUT Input Signals Table 11. Debug Port Timing Num Characteristic P61 DSCK Cycle Time P62 DSCK Clock Pulse Width P63 DSCK Rise ...
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... Figure 34. Debug Port Clock Input Timing CLKOUT Input Signals Figure 35. Debug Port Timings DSCK DSDI DSDO TSPC860 [Preliminary] 54 P59 P60 D64 D65 D66 D67 2129B–HIREL–12/04 ...
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Table 12. RESET Timing Num Characteristic R69 CLKOUT to HRESET high impedance R70 CLKOUT to SRESET high impedance R71 RSTCONF pulse width R72 – R73 Configuration Data to HRESET rising edge set up time R74 Configuration Data to RSTCONF rising ...
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... Figure 37. Reset Timing TSPC860 Data Bus Weak Drive during Configuration – CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 38. Reset Timing Debug Port Configuration IEEE 1149.1 Electrical Specifications – CLKOUT SRESET DSCK, DSDI TSPC860 [Preliminary] 56 R69 R79 R77 R78 R70 R82 R80 R80 ...
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Table 13. JTAG Timing Num Characteristic J82 TCK Cycle Time J83 TCK Clock Pulse Width Measured at 1.5V J84 TCK Rise and Fall Times J85 TMS, TDI Data Setup Time J86 TMS, TDI Data Hold Time J87 TCK Low to ...
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... Figure 41. JTAG TRST Timing Diagram – TCK TRST Figure 42. Boundary Scan (JTAG) Timing Diagram TCK Output Signals Output Signals Output Signals TSPC860 [Preliminary] 58 J91 J90 J92 J94 J93 J95 J96 2129B–HIREL–12/04 ...
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CPM Electrical Characteristics PIP/PIO AC Electrical Specifications Table 14. PIP/PIO Timing Num Characteristic 21 Data-In Setup Time to STBI Low 22 Data-In Hold Time to STBI High 23 STBI Pulse Width 24 STBO Pulse Width 25 Data-Out Setup Time to ...
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... Figure 44. PIP TX (Interlock Mode) Timing Diagram DATA OUT STBO (OUTPUT) STBI (INPUT) Figure 45. PIP RX (Pulse Mode) Timing Diagram DATA IN STBI (INPUT) STBO (OUTPUT) TSPC860 [Preliminary 2129B–HIREL–12/04 ...
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Figure 46. PIP TX (Pulse Mode) Timing Diagram DATA OUT STBO (OUTPUT) STBI (INPUT) Figure 47. Parallel I/O Data-in/Data-out Timing Diagram CLKO DATA IN DATA OUT 2129B–HIREL–12/ Table 15. Port C Interrupt Timing Number Characteristic ...
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... Figure 49. IDMA External Requests Timing Diagram CLKO (OUTPUT) DREQ (INPUT) Figure 50. SDACK Timing Diagram – Peripheral Write, TA Sampled Low at the Falling Edge of the Clock CLKO (OUTPUT) TS (OUTPUT) RD/WR (OUTPUT) DATA TA (OUTPUT) SDACK TSPC860 [Preliminary All Frequencies Min Max Unit 7 – – ns – ...
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Figure 51. SDACK Timing Diagram – Peripheral Write, TA Sampled High at the Falling Edge of the Clock CLKO (OUTPUT) TS (OUTPUT) RD/WR (OUTPUT) DATA TA (OUTPUT) SDACK Figure 52. SDACK Timing Diagram – Peripheral Read CLKO (OUTPUT) TS (OUTPUT) ...
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... TIN/TGATE Rise and Fall Time 62 TIN/TGATE Low Time 63 TIN/TGATE High Time 64 TIN/TGATE Cycle Time 65 CLKO High to TOUT Valid Figure 54. CPM General-Purpose Timers Timing Diagram CLKO 61 TIN/TGATE (INPUT) TOUT (OUTPUT) TSPC860 [Preliminary] 64 All Frequencies Min – All Frequencies Min ...
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Table 19. Serial Interface AC Electrical Specifications Number Characteristic 70 L1RCLK, L1TCLK Frequency (DSC = 0) 71 L1RCLK, L1TCLK Width Low (DSC = 0) 71A L1RCLK, L1TCLK Width High (DSC = 0) 72 L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time 73 ...
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... Figure 55. SI Receive Timing Diagram with Normal Clocking (DSC = 0) L1RCLK ( (Input) L1RCLK ( (Input) L1RSYNC (Input) 73 L1RXD (Input) L1ST(4-1) (Output) TSPC860 [Preliminary] 66 71A RFSD = BIT 2129B–HIREL–12/04 ...
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Figure 56. SI Receive Timing with Double-Speed Clocking (DSC = 1) L1RCLK ( (Input) 82 L1RCLK ( (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(1-4) (Output) L1CLKO (Output) ...
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... Figure 57. SI Transmit Timing Diagram (DSC = 0) 71 L1TCLK ( (Input) L1TCLK ( (Input) L1TSYNC (Input) L1TXD (Output) 78a L1ST(1-4) (Output) TSPC860 [Preliminary TFSD = 0 80a BIT 2129B–HIREL–12/04 ...
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Figure 58. SI Transmit Timing with Double Speed Clocking (DSC = 1) L1RCLK ( (Input) L1RCLK ( (Input) L1RSYNC (Input) L1TXD (Output) 80 L1ST(4-1) (Output) L1CLKO (Output) 2129B–HIREL–12/04 72 83a ...
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... Figure 59. IDL Timing TSPC860 [Preliminary] 70 2129B–HIREL–12/04 ...
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SCC In NMSI Mode Electrical Specifications Table 20. NMSI External Clock Timing Num Characteristic 100 RCLK1 and TCLK1 Width High 101 RCLK1 and TCLK1 Width Low 102 RCLK1 and TCLK1 Rise/Fall Time 103 TXD1 Active Delay (From TCLK1 Falling Edge) ...
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... CD1 (INPUT) CD1 (SYNC INPUT) Figure 61. SCC NMSI Transmit Timing Diagram 102 TCLK1 102 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (INPUT) CTS1 (SYNC INPUT) TSPC860 [Preliminary] 72 102 101 100 107 101 100 103 104 108 107 105 104 107 2129B–HIREL–12/04 ...
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Figure 62. HDLC Bus Timing Diagram TCLK1 102 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (ECHO INPUT) Table 22. Ethernet Electrical Specifications Number Characteristic 120 CLSN Width High 121 RCLK1 Rise/Fall Time 122 RCLK1 Width Low (1) 123 RCLK1 Clock Period 124 ...
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... Notes: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. TSPC860 [Preliminary] 74 120 121 121 124 125 ...
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Figure 66. CAM Interface Receive Start Timing Diagram RCLK1 RXD1 0 (Input) RSTRT (Output) Figure 67. CAM Interface REJECT Timing Diagram Table 23. SMC Transparent AC Electrical specifications Number Characteristic (1) 150 SMCLK Clock Period 151 SMCLK Width Low 151A ...
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... Master Data Setup Time (Inputs) 163 Master Data Hold Time (Inputs) 164 Master Data Valid (After SCK Edge) 165 Master Data Hold Time (Outputs) 166 Rise Time Output 167 Fall Time Output TSPC860 [Preliminary] 76 152 151 151a 150 (1) 155 155 153 All Frequencies ...
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Figure 69. SPI Master ( Timing Diagram 161 161 SPICLK OUTPUT 163 SPICLK OUTPUT 162 SPIMISO msb INPUT SPIMOSI OUTPUT MSB 167 Figure 70. SPI Master ( Timing Diagram 161 ...
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... Figure 71. SPI Slave ( Timing Diagram SPISEL INPUT 173 SPICLK INPUT SPICLK INPUT 177 180 SPIMISO MSBOUT OUTPUT 175 176 SPIMOSI MSBIN INPUT TSPC860 [Preliminary] 78 Min – 173 170 181 182 181 182 DATA LSBOUT 179 ...
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Figure 72. SPI Slave ( Timing Diagram SPISEL INPUT SPICLK INPUT 171 SPICLK INPUT 177 SPIMISO UNDEF OUTPUT SPIMOSI INPUT 2 Table 26 Electrical Specifications – SCL < 100 ...
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... STOP Condition Setup Time Notes: 1. SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) × pre_scaler The ratio SYNCCLK/(BRG_CLK/pre_scaler) must be greater or equal to 4/1. 2 Figure 73 Bus Timing Diagram SDA 202 205 SCL TSPC860 [Preliminary] 80 Expression fSCL (1) fSCL 203 204 207 209 206 ...
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... V and GND planes is recommended. DD All output pins on the TSPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflec- tions caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended ...
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... The TSPC860 PowerQUICC is comprised of three modules which all use the 32-bit internal bus: the Embedded PowerPC Core, the System Integration Unit (SIU), and the Communication Processor Module (CPM). The TSPC860 PowerQUICC block diagram is shown in Figure 1 ...
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... The TSPC860 PowerQUICC supports a wide range of power management features including Full On, Doze, Sleep, Deep Sleep, and Low Power Stop. In Full On mode the TSPC860 processor is fully powered with all internal units operating at the full speed of the processor. A Gear mode is provided which is determined by a clock divider, allowing the OS to reduce the operational frequency of the processor ...
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... The CPM contains features that allow the TSPC860 PowerQUICC to excel in communi- cations and networking products as did the TS68EN360 QUICC which preceded it. These features may be divided into three sub-groups: • ...
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... PowerPC architecture. • The addition of the MAC function to the TSPC860 CPM block to support the needs of higher performance communication software is the only major difference between the CPM on the TS68EN360 and that on the TSPC860. Therefore the registers used to initialize the QUICC CPM are similar to the TSPC860 CPM, but there are some minor changes necessary for supporting the MAC function ...
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... Avoid use of plastic, rubber, or silk in MOS areas f) Maintain relative humidity above 50% if practical Table 28. Package Description Package Designator ZP SQ/VR The TSPC860 uses × 25 mm, 357 pin Plastic Ball Grid Array (PBGA) package. The plastic package parameters are as provided in the following list. Package Outline Interconnects Pitch Solder Attach ...
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Package Dimensions Figure 75. Mechanical Dimensions and Bottom Surface Nomenclature of the ZP PBGA Package TOP VIEW ...
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... 910 Notes: 1. All dimensions in millimeters 2. Dimensions and tolerance per ASME Y14.5M, 1994 3. Maximum solder ball diameter measured parallel to Datum A TSPC860 [Preliminary 22.6 22.4 22.6 25 22.4 0.2 4X Top view (22.86) 18X 1.27 18X 1.27 (22.86) 0.9 357X ...
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Ordering Information Prefix Prototype Type Version SR Temperature range -55, +125˚C V: -40, +110˚C For availability of the different versions, contact your sales office Definitions Datasheet Status Objective Specification Target Specification Preliminary Specification site Preliminary Specification site Product ...
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... Document Revision History Table 29. Document Revision History Revision Number Substantive Change(s) Add ZQ package B See “Ordering Information” on page 89. A Initial revision TSPC860 [Preliminary] 90 Table 29 provides a revision history for this hardware specification. 2129B–HIREL–12/04 ...
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... Detailed Specifications ..................................................................... 28 Applicable Documents ...................................................................... 28 Design and Construction .................................................................................... 28 Terminal Connections ................................................................................. 28 Lead Material and Finish.............................................................................. 28 Package ...................................................................................................... 29 Absolute Maximum Ratings ................................................................................ 29 Absolute Maximum Rating for the TSPC860 .............................................. 29 Electrical Characteristics.................................................................. 30 General Requirements........................................................................................ 30 DC Electrical Specifications................................................................................ 30 AC Electrical Specifications Control Timing........................................................ 32 CPM Electrical Characteristics ......................................................... 59 PIP/PIO AC Electrical Specifications ...............................................59 SCC In NMSI Mode Electrical Specifications ...
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... Layout Practices ................................................................................................. 81 Functional Units Description............................................................ 82 Embedded PowerPC Core .................................................................................. 82 System Interface Unit (SIU) ................................................................................ 83 PCMCIA Controller ..................................................................................... 83 Power Management.................................................................................... 83 Communications Processor Module (CPM)................................................ 84 Software Compatibility Issues ............................................................................. 85 TSPC860 PowerQUICC Glueless System Design ............................................. 85 Preparation for Delivery ....................................................................86 Marking ............................................................................................................... 86 Packaging ........................................................................................................... 86 Certificate of Compliance..................................................................................... 86 Handling .............................................................................................................. 86 Package Mechanical Data .................................................................86 Package Parameters .......................................................................................... 86 Package Dimensions ...
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... Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 ® and combinations thereof are the registered trademarks of Atmel Corporation or its RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. ...