tspc860 ATMEL Corporation, tspc860 Datasheet - Page 79

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tspc860

Manufacturer Part Number
tspc860
Description
Integrated Communication Processor
Manufacturer
ATMEL Corporation
Datasheet
Figure 72. SPI Slave (CP = 1) Timing Diagram
Table 26. I
Notes:
2129B–HIREL–12/04
Number
200
200
202
203
204
205
206
207
208
209
210
211
SPIMISO
SPIMOSI
OUTPUT
SPICLK
SPICLK
SPISEL
INPUT
INPUT
INPUT
INPUT
1. SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3 × pre_scaler × 2)
Ci = 0
Ci = 1
The ratio SYNCCLK/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
2
C AC Electrical Specifications – SCL < 100 kHz
Characteristic
SCL Clock Frequency (SLAVE)
SCL Clock Frequency (MASTER)
LOW Period of SCL
HIGH Period of SCL
START Condition Setup Time
DATA Hold Time
DATA Setup Time
SDL/SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between Transmissions
START Condition Hold Time
SDL/SCL Rise Time
171
UNDEF
177
173
175
(1)
MSB
MSB
173
176
182
170
179
181
DATA
DATA
182
182
181
Min
250
1.5
4.7
4.7
4.0
4.7
4.0
4.7
0
0
172
All Frequencies
181
LSB
180
LSB
Max
100
100
300
178
1
174
MSB
MSB
Unit
KHz
KHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
79

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