tspc860 ATMEL Corporation, tspc860 Datasheet - Page 18

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
18
BADDR(28-
BADDR30
L1RXDB
L1TXDB
PA[15]
PA[14]
PA[13]
PA[12]
PA[11]
PA[10]
Name
RXD1
TXD1
RXD2
TXD2
REG
29)
AS
TSPC860 [Preliminary]
Reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Number
C18
D17
E17
G16
F17
J17
M3
M2
K4
L3
Bidirectional
Bidirectional
Open-drain)
Bidirectional
Bidirectional
Open-drain)
Bidirectional
Bidirectional
Open-drain)
(Optional:
(Optional:
(Optional:
Output
Output
Type
Input
Description
Burst Address 30—This output duplicates the value of A30 when the
following is true:
external bus
The memory controller uses BADDR30 to increment the address
lines that connect to memory devices when a synchronous external
master or an internal master initiates a burst transfer.
Register—When an internal master initiates an access to a slave
under control of the PCMCIA interface, this signal duplicates the
value of TSIZ0/REG. When an external master initiates an access,
REG is output by the PCMCIA interface (if it must handle the
transfer) to indicate the space in the PCMCIA card being accessed.
Burst Address—Outputs that duplicate A(28-29) values when one of
the following occurs:
external bus
The memory controller uses these signals to increment the address
lines that connect to memory devices when a synchronous external
or internal master starts a burst transfer.
Address Strobe—Input driven by an external asynchronous master
to indicate a valid address on A(0-31). The TSPC860 memory
controller synchronizes AS and controls the memory device
addressed under its control.
General-Purpose I/O Port A Bit 15—Bit 15 of the general-purpose
I/O port A.
RXD1—Receive data input for SCC1.
General-Purpose I/O Port A Bit 14—Bit 14 of the general-purpose
I/O port A.
TXD1—Transmit data output for SCC1. TXD1 has an open-drain
capability.
General-Purpose I/O Port A Bit 13—Bit 13 of the general-purpose
I/O port A.
RXD2—Receive data input for SCC2.
General-Purpose I/O Port A Bit 12—Bit 12 of the general-purpose
I/O port A.
TXD2—Transmit data output for SCC2. TXD2 has an open-drain
capability.
General-Purpose I/O Port A Bit 11—Bit 11 of the general-purpose
I/O port A.
L1TXDB—Transmit data output for the serial interface TDM port B.
L1TXDB has an open-drain capability.
General-Purpose I/O Port A Bit 10—Bit 10 of the general-purpose
I/O port A.
L1RXDB—Receive data input for the serial interface TDM port B.
An internal master in the TSPC860 initiates a transaction on the
A synchronous external master initiates a single beat transaction
An asynchronous external master initiates a transaction
An internal master in the TSPC860 initiates a transaction on the
An asynchronous external master initiates a transaction
A synchronous external master initiates a single beat transaction
2129B–HIREL–12/04