tspc860 ATMEL Corporation, tspc860 Datasheet - Page 38

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 7. Bus Operation Timings (Continued)
Notes:
38
Num
B41
B42
B43
1. Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
2. If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum values in
3. The timings specified in B4 and B5 are based on full strength clock.
4. The timing for BR output is relevant when the PC860 is selected to work with the external bus arbiter. The timing for BG out-
5. The timing required for BR input is relevant when the TSPC860 is selected to work with internal bus arbiter. The timing for
6. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is
7. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for
8. The timing B30 refers to CS when ACS = 00 and to WE (0:3) when CSNT = 0
9. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37
10. The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior speci-
Characteristic
TS valid to CLKOUT Rising Edge (SetUp Time).
CLKOUT Rising Edge to TS Valid (Hold Time).
AS negation to Memory Controller Signals
Negation
TSPC860 [Preliminary]
one cycle) or the frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then the maximum
allowed jitter on EXTAL can be up to 2%
put is relevant when the PC860 is selected to work with internal bus arbiter.
BG input is relevant when the TSPC860 is selected to work with internal bus arbiter.
asserted.
read accesses controlled by chip-selects under control of the UPM in the Memory Controller, for data beats where DLT3 = 1
in the UPM RAM words. (This is only the cases where data is latched on the falling edge of CLKOUT).
and B38 are specified to enable the freeze of the UPM output signals as described in Figure 22.
fied in Figure 25.
Figure 8. External Clock Timing
CLKOUT
Min
7
2
–
33 MHz
B4
Max
TBD
–
–
B1
B1
Min
7
2
–
40 MHz
B5
TBD
Max
–
–
Min
7
2
–
50 MHz
B3
Max
TBD
–
–
Min
B2
7
2
–
66 MHz
2129B–HIREL–12/04
Max
TBD
–
–
Unit
ns
ns
ns