tspc860 ATMEL Corporation, tspc860 Datasheet - Page 85

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Software Compatibility
Issues
TSPC860 PowerQUICC
Glueless System Design
2129B–HIREL–12/04
The following list summarizes the major software differences between the TS68EN360
QUICC and the TSPC860 PowerQUICC:
•
•
•
A fundamental design goal of the TSPC860 PowerQUICC was ease of interface to other
system components. Figure 72 on page 79 shows a system configuration that offers one
EPROM, one flash EPROM, and supports two DRAM SIMMs. Depending on the capac-
itance on the system bus, external buffers may be required. From a logic standpoint,
however, a glueless system is maintained.
Figure 74. TSPC860 System Configuration
Since the TSPC860 PowerQUICC uses an Embedded PowerPC Core, code written
for the TS68EN360 must be recompiled for the PowerPC instruction set. Code
which accesses the TS68EN360 peripherals requires only minor modifications for
use with the TSPC860. Although the functions performed by the PowerQUICC SIU
are similar to those performed by the QUICC SIM, the initialization sequence for the
SIU is different and therefore code that accesses the SIU must be rewritten. Many
developers of 68K compilers now provide compilers which also support the
PowerPC architecture.
The addition of the MAC function to the TSPC860 CPM block to support the needs
of higher performance communication software is the only major difference between
the CPM on the TS68EN360 and that on the TSPC860. Therefore the registers
used to initialize the QUICC CPM are similar to the TSPC860 CPM, but there are
some minor changes necessary for supporting the MAC function.
When porting code from the TS68EN360 CPM to the TSPC860 CPM, the software
writer will find new options for hardware breakpoint on CPU commands, address,
and serial request which are useful for software debugging. Support for single step
operation with all the registers of the CPM visible makes software development for
the CPM on the TSPC860 processor even simpler.
PowerQUICC
PC860
PRTY[3-0]
CAS[3-0]
WE[3-0]
Address
RAS2
RAS1
Data
CS7
CS0
OE
Buffer
RAS
CAS[3-0]
W (write)
Data
Address
Parity
E (Enable)
G (Output Enable)
W (Write)
Data
Address
WE (Write)
Data
Address
CE (Enable)
(Flash or Regular)
OE (Output Enable)
8, 16 or 32-bit
Two DRAM SIMMs
8-bit boot
(Optional Parity)
RAS
EPROM
SRAM
16 or 32 Bit
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