isp1507a NXP Semiconductors, isp1507a Datasheet
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isp1507a Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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... ISP1507A; ISP1507B ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 19 May 2008 1. General description The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 , On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 and UTMI+ Low Pin Interface (ULPI) Specification Rev ...
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... N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1507ABS) and 26 MHz (ISP1507BBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I Flexible system integration and very low current consumption, optimized for portable ...
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... Description HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 5 0. 0.85 mm © NXP B.V. 2008. All rights reserved. ...
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... GLOBAL CLOCKS 15 XTAL1 16 XTAL2 2, 22, 30 interface voltage V CC(I/O) 14 REG3V3 18 REG1V8 Fig 1. Block diagram ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B USB DATA SERIALIZER ULPI INTERFACE CONTROLLER USB DATA DESERIALIZER DRV V BUS V VALID BUS EXTERNAL REGISTER MAP DRV V BUS EXTERNAL POWER-ON RESET ...
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... LOW external V power switch or external charge pump enable BUS open-drain tolerant Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 24 DATA6 23 DATA7 22 V ...
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... PCB ground Section 7.9. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 16. © NXP B.V. 2008. All rights reserved ...
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... USB peripheral, host and OTG implementations. The following circuitry is included: • Differential drivers to transmit data at high-speed, full-speed and low-speed ISP1507A_ISP1507B_1 Product data sheet charge pump or external source BUS monitoring, charging and discharging Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 9. © NXP B.V. 2008. All rights reserved ...
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... SRP and HNP. ISP1507A_ISP1507B_1 Product data sheet high-speed bus terminations on DP and DM for peripheral and host modes Section 16. comparators to determine the V Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Table 8. CC < 3 voltage level. This is required for the V BUS © ...
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... BUS . Any voltage on V A_VBUS_VLD . hys(B_SESS_VLD) power. First, the B-device makes sure that V Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver . This is required for SRP. BUS . The downstream peripheral can draw its BUS valid comparator, session valid BUS voltage level. ...
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... C_A and C_B pins as shown in cp(C_A)-(C_B) load. The value of C BUS V BUS ISP1507 C_B C_A External capacitors connection 9. Section 9.3.1. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver at a nominal voltage BUS depends on the cp(C_A)-(C_B) Section 7.9.8. OTG V BUS 0 cp(C_A)-(C_B) 004aab037 ...
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... This provides an accurate voltage reference that overcurrent or fault circuit is used, the output fault indicator of that BUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 12, , must be connected between RREF RREF © ...
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... BUS power source by setting DRV_VBUS_EXT to logic 0. BUS comparators, and also as a power pin for the charge BUS to a voltage of 4 5.25 V, with a minimum output current BUS Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver C_A C cp(C_A)-(C_B) C_B V BUS I L ...
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... Product data sheet pin requires a capacitive load as shown in pin ( BUS VBUS VBUS Section Section 16. Section Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 16. must not be attached when using the ISP1507 16. Section 16. CC(I/O) 9.3.2. . © NXP B.V. 2008. All rights reserved. ...
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... ISP1507, except the charge pump. To ensure correct operation of the ISP1507, GND must be soldered to the cleanest ground available. ISP1507A_ISP1507B_1 Product data sheet 9.3.1. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 9.3.3. © NXP B.V. 2008. All rights reserved ...
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... DIR changes value. This is called the turnaround cycle. Data lines have fixed direction and different meaning in low-power and serial modes. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 15. A description of the ULPI pin Table 4 ...
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... To exit low-power mode, the link asserts the STP Direction Description O combinatorial LINESTATE0 directly driven by analog receiver O combinatorial LINESTATE1 directly driven by analog receiver Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver supply (see CC © NXP B.V. 2008. All rights reserved. Table 46 ...
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... O differential receive data from DP and DM O reserved; the ISP1507 will drive this pin to LOW Table Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Table 6. To enter 6-pin serial mode, the link sets Section 10.1.3) to logic enter 3-pin serial mode, the link sets the Section 10 ...
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... Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 8. Resistor setting signals are defined as follows: Internal resistor settings DM_PULL RPU_ RPD_ DOWN DP_EN DP_EN ...
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... Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver …continued Internal resistor settings DM_PULL RPU_ RPD_ RPD_ DOWN DP_EN DP_EN DM_EN ...
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... POR(trip) w(REG1V8_L PORP Internal power-on reset timing shows a typical start-up sequence. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver , for at least POR(trip) , and then rises above V POR(trip Figure 5 shows a possible curve of REG1V8. The , another POR pulse is ...
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... The link may start to detect DIR status level. If DIR is detected as LOW for three clock cycles, the link may send a RESET command. The ULPI interface is ready for use. ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver © NXP B.V. 2008. All rights reserved ...
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... If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will startup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver D RXCMD internal reset ...
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... ISP1507 was previously in serial or suspend mode, STP is used to exit. • The pull-down resistors on DATA[7:0] are disabled. • The ULPI controller is forced into an idle state and any ULPI command is ignored. ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Figure 7 applies only when CHIP_SELECT_N is asserted Hi-Z (link must drive) Hi-Z (input) Hi-Z (link must drive) Hi-Z (input) Rev. 01 — ...
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... DATA input ignored entering suspend mode Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver exiting 3-state mode exiting suspend mode 004aaa691 © NXP B.V. 2008. All rights reserved. 004aaa690 ...
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... V V fault detector circuits that output a digital fault BUS Section Section 10.1.3) to logic 1. For details, see Table 10. Any values other than those in Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 10.1.4). . BUS power sources are disabled BUS charge pump is enabled ...
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... XX XXXXb REGR voltage state: For an explanation of the V BUS Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Command description No operation. 00h is the idle value of the data bus. The link must drive NOOP by default. Transmit USB data that does not have a PID, such as chirp and resume signaling ...
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... High-speed Chirp squelch squelch !squelch !squelch and HS_Differential_Receiver_Output invalid !squelch and !HS_Differential_Receiver_Output invalid invalid Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Back-to-back RXCMDs turnaround turnaround RXCMD RXCMD © NXP B.V. 2008. All rights reserved. 004aaa695 ...
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... BUS A_VBUS_VLD V V BUS A_VBUS_VLD BUS voltage indicators, as shown in BUS 9.5.2.3. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Chirp squelch !squelch and HS_Differential_Receiver_Output !squelch and !HS_Differential_Receiver_Output invalid state field in the RXCMD is an encoding of the state are directly taken from ...
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... For standard hosts, the system must be able to provide in the range external circuit must be used to BUS sufficient level for operation. SESS_VLD must be enabled to detect the Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver (0, X) (1, 0) complement ...
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... When the ISP1507 has detected a SYNC pattern on the USB bus, it signals an When the ISP1507 has detected an error while receiving a USB packet, it HostDisconnect is encoded into the RxEvent field of the RXCMD. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section “Standard USB host controllers” RxError ...
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... D extended immediate register write register read shows the sequence of events for USB reset and high-speed detection . 0 Table 13. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver TXCMD (EXTW extended register read Figure 13 Section 10.1.2). © NXP B.V. 2008. All rights reserved. ...
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... OPMODE[1:0] to 00b and begins sending USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B . If the peripheral is in low-power mode, it must wake 0 Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver © ...
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... K (10b) (00b) TXCMD NOPID K K ... (HS) 10 (chirp) squelch peripheral chirp K (10b) (00b) Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver host chirp TXCMD (REGW) NOPID K J ... K J host chirp K (10b) or chirp J (01b) RXCMDs TXCMD (REGW) K ...
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... Table 18 for correct USB system operation. Examples of high-speed Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Figure 14. For details on USB ISP1507 ISP1507 asserts DIR, ISP1507 causing sends sends ...
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... Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) EOP link decision time ( clocks) Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver IDLE TXCMD TX start delay (one to two clocks) © ...
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... ISP1507A_ISP1507B_1 Product data sheet USB interpacket delay (8 to 192 high-speed bit times) IDLE N turnaround link decision time ( clocks) Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver TXCMD TX start delay (one to two clocks) Section 10.1.2). When in Figure 17. © NXP B.V. 2008. All rights reserved. ...
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... PRE ID DP and DM timing is not to scale. illustrates how a host or a hub places a full-speed or low-speed peripheral into Figure 18 timing is not to scale, and does not show all RXCMD Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver D1 D0 IDLE (min SYNC ...
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... RXCMD LINESTATE updates. ISP1507A_ISP1507B_1 Product data sheet suspend TXCMD TXCMD (REGW) NOPID J LINESTATE J LINESTATE K 00b J illustrates how a host or a hub places a high-speed enabled peripheral into Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver EOP resume K K ... K TXCMD K 10b K SE0 J SE0 J ...
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... The peripheral link sees terminations (TERMSELECT is set to 0b). The host link sets Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver terminations, and enables the 1.5 k terminations (TERMSELECT is set to © NXP B.V. 2008. All rights reserved. ...
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... Product data sheet FS suspend TXCMD TXCMD (REGW) NOPID 01b 00b FS J (01b) LINESTATE K LINESTATE J 01b 00b FS J (01b) Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver resume K HS idle TXCMD ... (REGW) 00b 10b 00b FS K (10b) SQUELCH (00b) ...
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... SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver © NXP B.V. 2008. All rights reserved ...
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... TXCMD (NOPID) type. The ISP1507 does not provide a mechanism to control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B TXCMD TXCMD NOPID 00h ...
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... The following subsections describe how to use the ISP1507 OTG components. ISP1507A_ISP1507B_1 Product data sheet 00h 00h 00h 80h PID SYNC PID BUS Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver ... ... D D FEh DATA PAYLOAD EOP IDLE 004aab125 © ...
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... For details, refer to UTMI+ Low Pin Interface (ULPI) Specification and Figure 23 provide examples of 6-pin serial mode and 3-pin serial mode, Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Section 7.6.4. When the controller is power by turning on the charge pump. BUS Section 9 ...
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... DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 23. Example of transmit followed by receive in 3-pin serial mode ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B TRANSMIT DATA EOP TRANSMIT DATA SYNC EOP Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver RECEIVE SYNC DATA ...
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... LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver © NXP B.V. 2008. All rights reserved ...
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... Size Address (6 bit) (bit) [1] [2] [ 00h to 3Fh 8 40h to FFh Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver References [ Section 10.1.1 on page 06h Section 10.1.2 on page 48 09h Section 10.1.3 on page 49 0Ch Section 10.1.4 on page 51 0Fh Section 10.1.5 on page 52 12h Section 10 ...
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... Value Description 15h Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h Table 25 RESET OPMODE[1: R/W/S/C R/W/S/C Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Table 22. Table Table 24 TERM XCVRSELECT[1:0] SELECT R/W/S/C R/W/S/C R/W/S/C © ...
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... Setting more than one of these fields results in undefined behavior. ISP1507A_ISP1507B_1 Product data sheet 8. Table 27 provides the bit allocation of the register. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver © NXP B.V. 2008. All rights reserved ...
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... Full-speed or low-speed packets are sent using the 6-pin serial interface. ISP1507A_ISP1507B_1 Product data sheet IND_ reserved COMPL R/W/S/C R/W/S/C Section 9.5.2.2. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 3 2 CLOCK_ reserved 3PIN_FSLS SUSPENDM _SERIAL 0 0 R/W/S/C R/W/S/C R/W/S/C state in RXCMD. For BUS Section 9 ...
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... DISCHRG_VBUS), and that both the DP and DM BUS (default). BUS . BUS : Discharges V through a resistor. If the link sets this bit to logic 1, it waits BUS BUS (default). BUS . BUS Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver DISCHRG_ DM_PULL DP_PULL VBUS DOWN DOWN R/W/S/C ...
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... Product data sheet Table 31 shows the bit allocation of the register ID_GND_R R/W/S/C R/W/S/C Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on Table 33. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver SESS_ SESS_ VBUS_ END_R VALID_R VALID_R R/W/S/C R/W/S/C R/W/S/C © ...
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... Session Valid: Reflects the current value of the session valid voltage comparator. V Valid: Reflects the current value of the V BUS Host Disconnect: Reflects the current value of the host disconnect detector. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 3 2 SESS_ SESS_ ...
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... ID_GND_L Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD reserved Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Table 37 SESS_ SESS_ VBUS_ END_L VALID_L VALID_L Table 39 ...
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... Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register. The functionality of the PHY will not be affected reserved R/W/S/C R/W/S/C Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Table 42 BVALID_ BVALID_ FALL RISE 0 ...
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... 1500 charge current discharge limit resistor resistance storage C S capacitor 100 pF Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver and GND) have a BUS Figure , see Section VBUS DEVICE UNDER TEST A B 0.1 F © NXP B.V. 2008. All rights reserved. ...
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... A LI all other pins; I < 0.5 V < V < +1 Conditions on pins STP, DATA[7:0], RESET_N and CHIP_SELECT_N on pins V , FAULT and PSW_N BUS on pins DP, DM and ID on pin XTAL1 . CC Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Max 0.5 +4.6 0.5 +4.6 0.5 V CC(I/O) 0.5 +6.0 0.5 +2.5 0.5 +4.6 [1] 0.5 +4.6 [2] 4 ...
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... ULPI interface pins are static = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions CC(I/ Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ 3.0 3.3 1.65 1.8 1 215 - [1] - ...
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... CC(I/O) amb Conditions CC(I/ +85 C; unless otherwise specified. amb Conditions external pull-up resistor connected external pull-up resistor connected Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ Max V 0 CC(I/ ...
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... Conditions includes V range DI pull-up on pin pull-down on pins DP and DM GND L for 1.5 k pull-up resistor includes V range DI pin to GND Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ Max 0 0 0.8 2 0.0 0.18 0.3 2.8 3.2 3.6 3.0 - 3.6 1425 1500 1575 ...
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... O(VBUS) comparators BUS = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions valid voltage for A-device and B-device Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ Max 14.25 15 15.75 14.25 15 15.75 [1] 40.5 45 49.5 [1] 40 ...
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... C; unless otherwise specified. CC(I/O) amb Conditions ID_PULLUP is logic +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ Max 281 680 - 656 1100 - 40 57 ...
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... I (mA) O(VBUS) Fig 26. V 004aaa878 I CC(cp) (mA) 3.4 3.5 3.6 V (V) CC(cp) Fig 28. Charge pump supply current as a function of Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 5. 3.3 V 3.0 V 5.00 4.50 4. O(VBUS) output voltage as a function of V BUS output current 108 ...
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... XTAL1 only for square wave input only for square wave input only for square wave input measured from power good or assertion of pin STP Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ 0 ...
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... C; unless otherwise specified. CC(I/O) amb Conditions pF pF excluding the first transition from the idle state Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Min Typ Max 5 7.8 4 ...
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... RX_DM; see Figure 32 DP RX_RCV, RX_DP and RX_DM; see Figure 32 DP RX_RCV, RX_DP and RX_DM; see Figure 32 DP RX_RCV, RX_DP and RX_DM; see Figure 32 Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver …continued Min Typ 1 ...
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... V OL 004aaa574 Fig 32. Timing of DP and DM to RX_RCV, RX_DP and CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver 0 PLH(drv) differential V CRS data lines 2 CRS 0 PLH(rcv) t PLH(se) ...
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... Remark: In the following application diagrams, because the ULPI bus is not shared, the CHIP_SELECT_N pin is connected to ground. In other applications, CHIP_SELECT_N can be controlled by a link to 3-state the ULPI bus so that those pins can be used for other purposes. ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Value Comment 0 mA), 270 nF (50 mA); ...
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... RECEPTACLE IP4359CX4/LF SHIELD ESD SHIELD 7 8 SHIELD 9 SHIELD C VBUS C bypass (1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz. Fig 34. Using the ISP1507 with an OTG controller; internal charge pump is utilized and crystal is attached V CC(I/O) DATA1 DATA0 DATA2 V CC(I/ RREF ...
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... C VBUS SHIELD 5 SHIELD IP4359CX4/ i(XTAL1) (1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz. Fig 35. Using the ISP1507 with a standard USB host controller; external 5 V source with built-in FAULT and external square wave input on XTAL1 V V CC(I/ bypass DATA1 DATA0 ...
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... D+ 3 USB STANDARD-B GND RECEPTACLE SHIELD IP4359CX4/ SHIELD 6 D ESD C bypass (1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz. Fig 36. Using the ISP1507 with a standard USB peripheral controller; external crystal V V CC(I/O) CC DATA1 DATA0 1 32 DATA2 V CC(I/ RREF RREF 3 30 ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION SOT617 ISSUE DATE ...
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... Solder bath specifications, including temperature and impurities ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 38. Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Figure 38) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Identification International Electrotechnical Commission Low-Speed Non-Return-to-Zero Inverted On-The-Go Printed-Circuit Board [1] Physical Layer Packet Identifier Programmable Logic Device Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver peak temperature 001aac844 © NXP B.V. 2008. All rights reserved. time ...
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... USB Implementers Forum UTMI+ Low Pin Interface USB 2.0 Transceiver Macrocell Interface USB 2.0 Transceiver Macrocell Interface Plus Data sheet status Product data sheet Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver Change notice Supersedes - - © NXP B.V. 2008. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 19 May 2008 ISP1507A; ISP1507B ULPI HS USB OTG transceiver © NXP B.V. 2008. All rights reserved ...
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... Table 32. USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description . .52 ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Table 33. USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 34. USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit description ...
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... FAULT and external square wave input on XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Fig 36. Using the ISP1507 with a standard USB peripheral controller; external crystal .71 ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B Fig 37. Package outline SOT617-1 (HVQFN32 Fig 38. Temperature profiles for large and small components Rev. 01 — 19 May 2008 ULPI HS USB OTG transceiver © ...
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... DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.16 STP 7.9.17 NXT 7.9.18 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9.19 CHIP_SELECT_N 7.9.20 GND (die pad Modes of operation . . . . . . . . . . . . . . . . . . . . . 15 ISP1507A_ISP1507B_1 Product data sheet ISP1507A; ISP1507B 8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 Synchronous mode . . . . . . . . . . . . . . . . . . . . 15 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 16 8.1.3 6-pin full-speed or low-speed serial mode . . . 17 8.1.4 3-pin full-speed or low-speed serial mode . . . 17 8.2 USB and OTG state transitions . . . . . . . . . . . 18 9 Protocol description . . . . . . . . . . . . . . . . . . . . 20 9 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: ISP1507A_ISP1507B_1 All rights reserved. Date of release: 19 May 2008 ...