peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 191

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RCE
RL(10:0)
Receive Length Check Enable
This bit is valid in HDLC mode only and enables/disables the receive
length check function:
RCE = ’0’
RCE = ’1’
Receive Length Check Limit
This bit-field defines the receive length check limit (32..65536 bytes) if
checking is enabled via bit ’RCE’:
RL(10:0)
No receive length check on received HDLC frames is
performed.
The receive length check is enabled. All bytes of a HDLC
frame which are transferred to the receive FIFO
(depending on the selected protocol sub-mode and
receive CRC handling) are counted and checked against
the maximum length check limit which is programmed in
bit field ’RL’.
A frame exceeding the maximum length is treated as if it
were aborted on the receive line (’RME’ interrupt and bit
’RAB’ (receive abort) set in the
In addition a ’FLEX’ interrupt is generated prior to ’RME’,
if enabled.
Note: The Receive Status Byte (RSTA) is part of the
The receive length limit is calculated by:
frame length checking.
5-191
Limit
=
Register Description (RLCRH)
(
RL
+
RSTA
1
) 32
×
byte).
PEB 20525
PEF 20525
2000-09-14