peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 59

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Figure 21
The common transmit and receive clock is supplied at pin RxCLK and the common frame
synchronisation signal at pin FSC. The "strobe signals" for active time slots are
generated internally by the time slot assigner block (TSA) independent in transmit and
receive direction.
When the transmit and receive PCM masks are enabled, bit fields ’TCC’ and ’RCC’ are
ignored because of the constant 8-bit time slot width.
Data Sheet
RxCLK
time slot
active
FSC
TTSA0..3: Transmit Time Slot Assignment Register
7
PCMTX0..3: Transmit PCM Mask Register
31
RTSA0..3: Receive Time Slot Assignment Register
7
PCMRX0..3: Receive PCM Mask Register
31
TS delay (transmit):
1 + TTSN*8 + TCS
(1..1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1..1024)
PCMTX3
PCMRX3
Selecting one or more time-slots of 8-bit width
RTSA3
TTSA3
...
24 23
24 23
0
0
7
7
RCC
TCC
PCMTX2
PCMRX2
RTSA2
TTSA2
8 bit
TS0
17
1
TS1
59
16 15
16 15
0
0
7
7
1
1
TS2
TEPCM = '1': TPCM Mask Enabled
REPCM = '1': TPCM Mask Enabled
TS3
PCMRX1
PCMTX1
RTSA1
TTSA1
RTSN
TTSN
TS4
TS5
0
0
8 7
8 7
7
7
Functional Overview
TS16 TS17
PCMTX0
PCMRX0
TTSA0
RTSA0
1
3
PEB 20525
PEF 20525
2000-09-14
RCS
TCS
0
0
0
0