peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 8

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

List of Figures
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Data Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System Integration With External DMA Controller . . . . . . . . . . . . . . . . 22
Point-to-Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multimaster Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin Configuration P-LFBGA-80-2 Package . . . . . . . . . . . . . . . . . . . . . 26
Pin Configuration P-TQFP-100-3 Package . . . . . . . . . . . . . . . . . . . . . 27
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . 46
XFIFO/RFIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . 46
Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Selecting one time-slot of programmable delay and width . . . . . . . . . 57
Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . 59
Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . 62
Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . 64
Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) . . . 70
DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) . . . 70
DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . . 71
Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
HDLC Receive Data Processing in 16 bit Automode . . . . . . . . . . . . . . 86
HDLC Receive Data Processing in 8 bit Automode . . . . . . . . . . . . . . . 86
HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . . 86
HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . . 87
8
PEB 20525
PEF 20525
2000-09-14
Page