peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 32

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
P-
LFBGA-
80-2
H9
H2
Data Sheet
P-TQFP-
100-3
54
19
Microprocessor Bus Interface
Symbol In (I)
READY
DTACK
RESET I
Out (O)
O
O
Function
Ready (Intel bus mode)
Data Transfer Acknowledge (Motorola mode)
During a slave access (register read/write) this
signal (output) indicates, that the SEROCCO-H is
ready for data transfer. The signal remains active
until the data strobe (DS in Motorola bus mode,
RD/WR in Intel bus mode) and/or the chip select
(CS) go inactive.
This line is tri-state when unused.
A pull-up resistor to V
function is not used.
Reset
With this active low signal the on-chip registers
and state machines are forced to reset state.
During Reset all pins are in a high impedance
state.
32
DD3
is recommended if this
Pin Descriptions
PEB 20525
PEF 20525
2000-09-14