peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 219

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

6.3
The following table provides a definition of terms used in this chapter to describe the
operation with external DMA controller support.
Table 17
Packet
Buffer
Block
Bus Cycle
DMA Transfer
6.3.1
Any packet transmission is prepared by initializing the external DMA controller with the
transmit buffer start address and writing the packet size in number of bytes to registers
XBCL/XBCH.
Now there are two possible scenarios:
• If the prepared transmit buffer in memory contains a complete packet, the start
• If a transmit packet is distributed over more than one transmit buffer in memory, the
Data Sheet
command for DMA transmission is issued by setting bits ’XF’ and ’XME’ in register
XBCH
transfer data into the XFIFO . After the last byte has been transmitted, the protocol
machine appends the trailer (e.g. CRC and Flag in HDLC), if applicable. The Transmit
DMA Transfer End (TDTE) interrupt is generated (refer to
’XF’ command (without setting the ’XME’ bit) forces SEROCCO-H to request data
transfers from the external DMA controller from this buffer. A Transmit DMA Transfer
to ’1’. The DMA support logic will request the external DMA controller to
External DMA Supported Mode
Data Transmission (With External DMA Support)
DMA Terminology
A "Packet" is a connected block of data bytes. If a receive
status byte (RSTA) is attached to data bytes, it is also
considered as part of the packet.
A "Buffer" is a limited space in memory that is reserved for
DMA reception/transmission. SEROCCO-H can optionally
keep track of predefined (receive) buffer limits and notify
the CPU with an appropriate interrupt if this functionality is
not provided by the external DMA controller.
A packet can go into one single buffer, or it can go
fragmented into multiple buffers.
A "Block" is the amount of data that is transfered from the
memory to the XFIFO (transmit DMA transfer) or from the
RFIFO to the memory. The block size is 32 bytes by
default. It can be lowered with the receive FIFO threshold
in register CCR3H, bit field ’RFTH(1..0)’.
A "Bus Cycle" corresponds to a single byte/word transfer.
Multiple bus cycles make up a block transfer.
A "DMA Transfer" is the movement of complete buffers
and/or packets between the XFIFO/RFIFO and the
memory by the external DMA controller.
219
Figure
55).
Programming
PEB 20525
PEF 20525
2000-09-14