is42s16800a1 Integrated Silicon Solution, Inc., is42s16800a1 Datasheet - Page 13

• Manufacturer Part Number: is42s16800a1
• Description: 8meg 128-mbit Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.
The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the
first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining
data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-
ished, any additional data supplied to the DQ pins will be ignored.
Burst Write Operation
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-
rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-
grammed burst length is satisfied.
Write Interrupted by a Write
IS42S16800A1
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00B
05/01/06
CK
COMMAND
DQs
CK
COMMAND
DQs
: “H” or “L”
are registered on the same clock edge.
The first data element and the Write
T0
T0
NOP
NOP
WRITE A
T1
WRITE A
T1
DIN A
DIN A
1 CK Interval
0
0
WRITE B
T2
T2
DIN B
NOP
DIN A
0
1
T3
T3
NOP
DIN B
NOP
DIN A
1
2
1-800-379-4774
T4
T4
NOP
DIN B
NOP
DIN A
Extra data is masked.
2
3
T5
T5
NOP
DIN B
NOP
(Burst Length = 4, CAS latency = 2, 3)
N
(
3
Burst Length = 4, CAS latency = 2, 3)
T6
T6
NOP
NOP
©
T7
T7
NOP
NOP
T8
T8
NOP
NOP
ISSI
13
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