is42s16800a1 Integrated Silicon Solution, Inc., is42s16800a1 Datasheet - Page 27

• Manufacturer Part Number: is42s16800a1
• Description: 8meg 128-mbit Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

Clock Suspend during a Write Cycle
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks
is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”
any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and
the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands
that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE
returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto
the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-
pend mode is exited.
IS42S16800A1
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00B
05/01/06
CK
CKE
COMMAND
DQs
CK
CKE
COMMAND
DQs
: “H” or “L”
: “H” or “L”
T0
T0
NOP
NOP
WRITE A
T1
T1
READ A
DIN A
0
T2
T2
NOP
NOP
DIN A
1
T3
T3
DOUT A
NOP
NOP
DIN A
2
DIN is masked during the Clock Suspend Period
0
1-800-379-4774
T4
T4
A one clock delay before
A one clock delay before
suspend operation starts
suspend operation starts
suspend operation starts is held valid
DOUT element at the DQs when the
T5
T5
N
(Burst Length = 4, CAS Latency = 2)
(Burst Length = 4, CAS Latency = 2)
DOUT A
T6
T6
1
A one clock delay to exit
A one clock delay to exit
the Suspend command
the Suspend command
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T7
T7
NOP
NOP
DIN A
3
T8
T8
DOUT A
NOP
NOP
ISSI
2
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