is43dr16128 Integrated Silicon Solution, Inc., is43dr16128 Datasheet
is43dr16128
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is43dr16128 Summary of contents
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... Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized ...
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... DLL ground ODT On Die Termination Enable NC No connect Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 Note: VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from ...
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... To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 1 at a LOW state (all other inputs may be ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 A12 Active ...
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... Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 Qoff A12 Output ...
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... Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3]. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 High Temperature Self-Refresh Rate Enable ...
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... Self refresh exit is asynchronous. 8. VREF must be maintained during Self Refresh operation. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 CKE CS# RAS# CAS# Current ...
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... Write Inhibit Note: 1. Used to mask write data, provided coincident with the corresponding data. Functional Block Diagram Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 CKE Command (N) (1) RAS#, CAS#, WE#, CS# Current ...
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... REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#‐before‐RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent, so it must be issued each time a refresh is Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ...
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... EMRS to ODT Update Delay CK EMRS Command ~ ODT tAOFD Old Setting Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 NOP NOP tMOD(Max) tMOD(Min) ~ NOP NOP NOP ~ ~ ...
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... ODT Timing for Precharge Power‐Down Mode Note: Both ODT to Power Down Endtry and Exit Latencies tANPD and tAXPD are not met, therefore Power‐Down Mode timings have to be applied. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 12 ...
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... Thermal Resistance Airflow = 0m/s Theta‐ja 59.4 Theta‐jc 0.1 Note: 4‐layer PCB Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 Parameter Min. 1.7 1.7 1.7 0.49*VDDQ VREF‐0.04 ...
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... Refer to Overshoot and Undershoot Specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 Min. VREF + 0.125 ...
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... Note: Please refer to AC Overshoot and Undershoot Definition Diagram. AC Overshoot and Undershoot Definition Diagram Volts ( Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 V DDQ SSQ 0.5 x VDDQ‐0.125 DDR2‐533 ...
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... Input Capacitance (all other input‐only pins) Input Capacitance Delta (all other input‐only pins) I/O Capacitance (DQ, DM, DQS, DQS#) I/O Capacitance Delta (DQ, DM, DQS, DQS#) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 Parameter Parameter Parameter ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 Symbol ...
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... Legend: A=Activate, RA=Read with Auto‐Precharge, D=DESELECT. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 . MRS A12 bit is set to ...
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... IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Parametric Test Condition. 3. IDD parameters are specified with ODT disabled. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ‐3D ‐25E/25D DDR2‐667D ...
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... Data Hold Skew tQHS Factor Clock Half Period tHP Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ‐37C ‐3D ‐25E DDR2‐533C DDR2‐667D ...
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... Data‐Out to High tHZ Impedance from CK/CK# DQS/DQS# Low tLZ(DQS) Impedance from CK/CK# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ‐37C ‐3D ‐25E DDR2‐533C DDR2‐667D DDR2‐800E ...
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... The CK/CK# input reference level (for timing reference to CK/CK#) is the point at which CK and CK# cross the DQS/DQS# input reference level is the cross point when in differential strobe mode; the input reference level for signals other than CK/CK#, or DQS/DQS# is VREF. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ‐ ...
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... Applicable to certain temperature grades. Specified OPER (Tc and Ta) must not be violated for each temperature grade. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 24 ...
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... A CL‐t ‐t Order Part No. 5‐5‐5 IS43DR16128‐3DBLI IS43DR16128‐3DBI = ‐40°C to +85°C A CL‐t ‐t Order Part No. 5‐5‐5 IS46DR16128‐3DBLA1 ...
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... IS43/46DR16128 84-ball FBGA: Fine Pitch Ball Grid Array Outline Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B, 3/28/2011 26 ...