is43lr32200b-6bl Integrated Silicon Solution, Inc., is43lr32200b-6bl Datasheet - Page 31

• Manufacturer Part Number: is43lr32200b-6bl
• Description: 512k X 32bits X 4banks Mobile Ddr Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Rev. 00A | Feb. 2011
Write
select the starting column location.
precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. Input data
appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given
DM signal is registered low, the corresponding data will be written to the memory; if the DM signal is registered high, the corresponding
data-inputs will be ignored, and a write will not be executed to that byte/column location. The memory controller drives the DQS during
write operations. The initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z and any additional input
data will be ignored.
Figure20 : Write command
Figure21 : Write Burst (BL=4)
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs
The value of A10 determines whether or not auto precharge is used.If autoprecharge is selected, the row being accessed will be
Notes:
1. Din n = Data-In from Column n.
Command
Address
/CLK
DQS
CLK
DM
DQ
WRITE
Bank a
COL n
T0
tWPRES
BA0, BA 1
Don ’ t care
tDQSS
A0~A7
/CLK
/RAS
/CAS
/WE
CLK
CKE
A10
/CS
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T1
NOP
D
n
IN
tWPRE
tDQSH
CA
BA
T1n
n+1
D
IN
tDS
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WRITE
Bank a
COL m
n+2
T2
D
IN
tDH
T2n
Don ’ t care
n+3
D
IN
tWPST
Notes :
1. CA : Column address
2. BA : Bank address
3. A10=High : Enable Auto precharge
T3
A10=Low : Disable Auto precharge
IS43/46LR32200B
Advanced Information
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