tc58dvm92a5baj3

Manufacturer Part Numbertc58dvm92a5baj3
Description512-mbit 64m ? 8 Bits Cmos Nand E Prom Description
ManufacturerTOSHIBA Semiconductor CORPORATION
tc58dvm92a5baj3 datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Page 1/36

Download datasheet (261Kb)Embed
Next
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M × 8 BITS) CMOS NAND E
DESCRIPTION
The device is a single 3.3 V 512Mbit (553,648,128 bit) NAND Electrically Erasable and Programmable Read-Only
2
Memory (NAND E
PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte static
register which allows program and read data to be transferred between the register and the memory cell array in
528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ×
32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell allay 528 × 128K × 8
Register
528 × 8
Page size
528 bytes
(16K + 512) bytes
Block size
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
Mode control
Serial input/output
Command control
Power supply
V
= 2.7 V to 3.6 V
CC
Access time
Cell array to register 25 µs max
Serial Read Cycle
40 ns min
Program/Erase time
Auto Page Program 300 µs/page typ.
Auto Block Erase
2.5 ms/block typ.
Operating current
Read (40 ns cycle)
20 mA max.
Program (avg.)
20 mA max.
Erase (avg.)
20 mA max.
Standby
50 µA max
Package
P-TFBGA63-0813-0.80AZ (Weight: 0.16 g typ.)
TC58DVM92A5BAJ3
2
PROM
1
2010-06-16

tc58dvm92a5baj3 Summary of contents

  • Page 1

    ... Program/Erase time Auto Page Program 300 µs/page typ. Auto Block Erase 2.5 ms/block typ. • Operating current Read (40 ns cycle max. Program (avg max. Erase (avg max. Standby 50 µA max • Package P-TFBGA63-0813-0.80AZ (Weight: 0.16 g typ.) TC58DVM92A5BAJ3 2 PROM 1 2010-06-16 ...

  • Page 2

    ... Read enable CLE Command latch enable ALE Address latch enable WP Write protect Ready/Busy V Power supply CC V Ground connection RY I/O6 I/O8 CC I/O5 I/ TC58DVM92A5BAJ3 2010-06-16 ...

  • Page 3

    ... This parameter is periodically sampled and is not tested for every device. * Status register Address register Command register Control HV generator RATING PARAMETER CONDITION OUT 3 TC58DVM92A5BAJ3 Column buffer Column decoder Data register Sense amp Memory cell array VALUE − 0.6 to 4.6 − 0.6 to 4.6 − ≤ 4 ...

  • Page 4

    ... − − 400 µ 2 0 pin TC58DVM92A5BAJ3 MIN TYP. MAX ⎯ 4016 4096 MIN TYP. MAX ⎯ 2.7 3.6 × 0.78 ⎯ − 0.3 * ⎯ × 0. MIN TYP. MAX ⎯ ...

  • Page 5

    ... WE High to Busy WB t ALE Low to RE Low (Read Cycle) AR2 t Device Reset Time (Ready/Read/Program/Erase) RST *1: tCLS and tALS can not be shorter than tWP *2: tCS should be longer than tWP + 10ns. PARAMETER 5 TC58DVM92A5BAJ3 MIN MAX UNIT NOTES ⎯ ⎯ ⎯ ⎯ ...

  • Page 6

    ... PROGRAMMING AND ERASING CHARACTERISTICS (Ta = -40° to 85° SYMBOL PARAMETER t Programming Time PROG Number of Programming Cycles on Same N Page t Block Erasing Time BERASE (1): Refer to Application Note (12) toward the end of this document. TC58DVM92A5BAJ3 CONDITION 2.7V to 3.6V − 0 (100 pF TTL C L MIN TYP ...

  • Page 7

    ... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O Setup Time CLH ALH TC58DVM92A5BAJ3 Hold Time 2010-06-16 ...

  • Page 8

    ... A16 ALS TC58DVM92A5BAJ3 ALH A17 to A24 A25 : CLH ...

  • Page 9

    ... REH RHZ RHZ REA CLR t CLH WHC CEA t WHR 70h * 9 TC58DVM92A5BAJ3 CHZ t RHZ t t REA OH t CEA t CHZ REA RHZ Status output : 2010-06-16 ...

  • Page 10

    ... A17 A25 to A24 ALH AR2 A17 A25 to A24 10 TC58DVM92A5BAJ3 REA OUT OUT OUT OUT 527 : CHZ REA t RHZ OUT ...

  • Page 11

    ... Read operation using 50h command ALH A17 A25 to A16 to A24 ALH A17 A25 to A16 to A24 TC58DVM92A5BAJ3 t AR2 REA D D OUT OUT 256 + N 256 + AR2 REA D D ...

  • Page 12

    ... Do not input data while data is being output ALH WB BERASE A25 D0h Erase Start Busy command : not input data while data is being output TC58DVM92A5BAJ3 t PROG 10h 70h 527 Status 70h output Status Read command 2010-06-16 ...

  • Page 13

    ... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O 90h CEA t t ALH ALEA t REA 00h 98h Address Maker code input 13 TC58DVM92A5BAJ3 t REA 76h Device code : 2010-06-16 ...

  • Page 14

    ... H) after completion of the operation. The output buffer for this signal is an open drain and has pulled-up to Vccq with an appropriate resister L), such as during a Program or Erase or Read operation, and after the falling edge REA 14 TC58DVM92A5BAJ3 signal is in 2010-06-16 ...

  • Page 15

    ... Table 1. I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 * TC58DVM92A5BAJ3 I/ A7: Column address A25: Page address A9 A14 to A25: Block address A9 to A13: NAND address in block A17 A25 2010-06-16 ...

  • Page 16

    ... CLE ALE L), such as during a Program or Erase or Read operation, CE input goes High. ALE TC58DVM92A5BAJ3 * V I/O1 to I/O8 Power L Data output Active H High impedance Active 2010-06-16 ...

  • Page 17

    ... Reset FF Auto Program 10 Auto Block Erase 60 Status Read 70 ID Read 90 Second Cycle Acceptable while Busy ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ D0 ⎯ ⎯ 17 TC58DVM92A5BAJ3 HEX data bit assignment (Example) Serial data input: 80h I/ I/O1 2010-06-16 ...

  • Page 18

    ... Busy N M 527 The operation of the device after input of the 01h command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). Cell array 18 TC58DVM92A5BAJ3 2010-06-16 ...

  • Page 19

    ... Once a 50h command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the address. (An 00h or an 01h command is necessary to move the pointer back to the 0 to 511 main memory cell location.) 19 TC58DVM92A5BAJ3 2010-06-16 ...

  • Page 20

    ... Busy 70h Status on Device 1 Figure 5. Status Read timing application example pin signals from multiple devices are wired together as shown in the 20 TC58DVM92A5BAJ3 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device ...

  • Page 21

    ... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Erase Start command Busy 21 TC58DVM92A5BAJ3 Pass 70 I/O Status Read Fail command automatically returns to Ready after completion of the operation ...

  • Page 22

    ... RST (max 5 µ RST command is invalid, but the third 22 TC58DVM92A5BAJ3 Figure 7. 00 Figure 8. 00 (max 500 µ s) RST Figure 9. 00 Figure 10. I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy Figure 11. ( command is valid ...

  • Page 23

    ... Table 6. ID Codes read out by ID read command 90h I/O8 Maker code 1 Device code 0 t CEA t ALEA t REA 00h 98h Maker code 00h Figure 12. ID Read timing I/O7 I/O6 I/O5 I/ TC58DVM92A5BAJ3 76h Device code I/O3 I/O2 I/O1 Hex Data 98h 76h 2010-06-16 ...

  • Page 24

    ... During Busy state, do not input any command except 70h and FFh. reaches 2.5 V and CE signal is kept high 1ms max Operation becomes 2.5V, it should begin access after about 1ms. CC Figure 13. Power-on/off Sequence FF Reset Figure 14. 24 TC58DVM92A5BAJ3 Don’t care V IL Don’t care 2010-06-16 ...

  • Page 25

    ... For this operation the “FFh” command is needed. Programming cannot be executed. Ex.) Random page program (Prohibition) DATA IN: Data (1) (1) Page 0 (2) Page 1 Page 2 (3) Page 15 Page 31 Figure 15. page programming within a block 70 Status Read command input Figure 16. 25 TC58DVM92A5BAJ3 Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2010-06-16 ...

  • Page 26

    ... Add Start point C area 00h Add Start point A area 10h DIN Start point C Area 10h DIN Start point B Area 26 TC58DVM92A5BAJ3 255 256 511 512 A B Pointer control Figure 17 Pointer control 50h Add Start point C area 00h Add Start point A area ...

  • Page 27

    ... Ready 1.5 µ s 1.0 µ 0.5 µ Ω 27 TC58DVM92A5BAJ3 buffer consists of an open drain Busy 3 25° 100 Ω Ω Ω ...

  • Page 28

    ... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TC58DVM92A5BAJ3 2010-06-16 ...

  • Page 29

    ... Although the device may read in a fifth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00h, 01h or 50h Internal read operation starts when WE goes High in the fourth cycle. Program operation CLE CE WE ALE I/O 80h Address input Figure 20. Address input ignored Figure 21. 29 TC58DVM92A5BAJ3 ignored Data input 2010-06-16 ...

  • Page 30

    ... Busy state. (Refer to Figure 23.) I/O 00h/01h/50h Hence the RE clock input must start after the address input. All 1 s Data Pattern 2 All 1 s Data Pattern 2 Figure 22 Address input Figure 23. 30 TC58DVM92A5BAJ3 All 1 s Data Pattern 3 Data Pattern 3 2010-06-16 ...

  • Page 31

    ... Read Check: Read column 517 of the 1st page Start Block Fail Read Check Pass Block No. = 4096 Yes End Figure 25 31 TC58DVM92A5BAJ3 TYP. MAX UNIT ⎯ 4096 Block in the block. If the column is not FFh , define the block as a bad block. Bad Block * 1 ...

  • Page 32

    ... Status Read after Program → Block Replacement ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 26. 32 TC58DVM92A5BAJ3 2010-06-16 ...

  • Page 33

    ... After a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure and reprogramming, the block may become usable again. TC58DVM92A5BAJ3 33 2010-06-16 ...

  • Page 34

    ... Package Dimensions Weight: 0.16 g (typ.) TC58DVM92A5BAJ3 34 Unit : mm 2010-06-16 ...

  • Page 35

    ... Revision History Date Rev. Description 2009-11-24 1.00 Original version Described ECC as 1 bit correction per 512 Bytes. 2010-04-23 1.01 Changed package drawing. 2010-06-16 1.02 TC58DVM92A5BAJ3 35 2010-06-16 ...

  • Page 36

    ... Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. TC58DVM92A5BAJ3 36 2010-06-16 ...