c8051f544 Silicon Laboratories, c8051f544 Datasheet - Page 114

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c8051f544

Manufacturer Part Number
c8051f544
Description
Mixed Signal Isp Flash Mcu Family
Manufacturer
Silicon Laboratories
Datasheet

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C8051F54x
SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2
SFR Address = 0xF7; SFR Page = 0x00 and 0x0F
114
Name
Reset
7:3
Bit
Type
2
1
0
Bit
Unused
Unused
PREG0
Name
PMAT
R
7
0
Read = 00000b; Write = Don’t Care.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
Read = 0b; Write = Don’t Care.
Voltage Regulator Dropout Interrupt Priority Control.
This bit sets the priority of the Voltage Regulator Dropout interrupt.
0: Voltage Regulator Dropout interrupt set to low priority level.
1: Voltage Regulator Dropout interrupt set to high priority level.
R
6
0
R
5
0
Rev. 1.0
R
4
0
Function
R
3
0
PMAT
R/W
2
0
R
1
0
PREG0
R/W
0
0

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