c8051f544 Silicon Laboratories, c8051f544 Datasheet - Page 28

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c8051f544

Manufacturer Part Number
c8051f544
Description
Mixed Signal Isp Flash Mcu Family
Manufacturer
Silicon Laboratories
Datasheet

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C8051F54x
28
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Dimension
metal pad is to be 60 m minimum, all the way around the pad.
good solder paste release.
pad.
Components.
C1
C2
X1
E
Table 4.6. QFN-24 Landing Diagram Dimensions
 
3.90
3.90
0.20
Min
Figure 4.6. QFN-24 Landing Diagram
0.50 BSC
Max
4.00
4.00
0.30
Rev. 1.0
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80

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