c8051f544 Silicon Laboratories, c8051f544 Datasheet - Page 168

• Manufacturer Part Number: c8051f544
• Description: Mixed Signal Isp Flash Mcu Family
• Manufacturer: Silicon Laboratories

C8051F54x
SFR Definition 18.25. P3MDIN: Port 3 Input Mode
SFR Address = 0xF4; SFR Page = 0x0F
SFR Definition 18.26. P3MDOUT: Port 3 Output Mode
SFR Address = 0xAE; SFR Page = 0x0F
168
Note: Port P3.0 is only available on the 32-pin packages.
Note: Port P3.0 is only available on the 32-pin packages.
Name
Reset
Name
Reset
7:1
7:1
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.0.
Bit
Bit
Type
Type
0
Bit
Bit
P3MDIN[0]
Unused
Unused
Name
Name
R
7
0
R
7
1
Read = 0000000b; Write = Don’t Care.
Analog Configuration Bits for P3.0.
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P3MDOUT register.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
Read = 0000000b; Write = Don’t Care.
These bits are ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
R
6
0
R
6
1
R
5
0
R
5
1
R
4
0
Rev. 1.0
R
4
1
R
3
0
Function
Function
R
3
1
R
2
0
R
2
1
R
1
0
R
1
1
P3MDOUT[0]
P3MDIN[0]
R/W
R/W
0
0
0
1