c8051f544 Silicon Laboratories, c8051f544 Datasheet - Page 199

• Manufacturer Part Number: c8051f544
• Description: Mixed Signal Isp Flash Mcu Family
• Manufacturer: Silicon Laboratories

20.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data. An interrupt is generated after each received byte.
Software must write the ACK bit at that time to ACK or NACK the received byte. Writing a 1 to the ACK bit
generates an ACK; writing a 0 generates a NACK. Software should write a 0 to the ACK bit for the last data
transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a
STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an
active Master Receiver. Figure 20.6 shows a typical master read sequence. Two received data bytes are
shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts
occur before the ACK cycle in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 20.6. Typical Master Read Sequence
R
A
Data Byte
Interrupts
Rev. 1.0
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
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P
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