c8051f544 Silicon Laboratories, c8051f544 Datasheet - Page 39

• Manufacturer Part Number: c8051f544
• Description: Mixed Signal Isp Flash Mcu Family
• Manufacturer: Silicon Laboratories

Gain Register Definition 5.3. ADC0GNA: ADC0 Additional Selectable Gain
Indirect Address = 0x08;
Note: This register is accessed indirectly; See
Name Reserved
Reset
Bit
7:1
Type
0
Bit
GAINADD
Reserved
Name
W
7
0
ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Must Write 0000000b.
Reserved
W
6
0
Reserved
W
5
0
Section 5.3.2
Reserved
Rev. 1.0
W
4
0
for details for writing this register.
Function
Reserved
W
3
0
Reserved
W
2
0
C8051F54x
Reserved GAINADD
W
1
0
W
0
1
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