cop8tab9 National Semiconductor Corporation, cop8tab9 Datasheet - Page 14

• Manufacturer Part Number: cop8tab9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
9.0 Pin Descriptions
CKI is the clock input. This pin can be connected (in con-
junction with CKO) to an external crystal circuit to form a
crystal oscillator, to an external resistor for RC oscillator
operation or to an external clock. See Oscillator Description
section.
RESET is the master reset input. See Reset description
section.
The device contains up to five bidirectional 8-bit I/O ports (C,
F, G, J and L), where each individual bit may be indepen-
dently configured as an input (Schmitt trigger inputs on all
ports), output or TRI-STATE under program control. Three
data memory address locations are allocated for each of
these I/O ports. Each I/O port has three associated 8-bit
memory mapped registers, the CONFIGURATION register,
the output DATA register and the Pin input register. (See the
memory map for the various addresses associated with the
I/O ports.) Figure 6 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port bit
to be individually configured under software control as
shown below:
Port C supports the Multi-Input Wake-Up feature on all eight
pins. Port C is not available on 20 and 28 pin packages.
When using these packages, the user should ensure that
Port C Multi-Input Wake-Up is disabled by clearing the
CWKEN Register to prevent spurious interrupts and
wake-up events. Port C has the following alternate pin func-
tions:
C7 Multi-Input Wake-Up
C6 Multi-Input Wake-Up
C5 Multi-Input Wake-Up
C4 Multi-Input Wake-Up
C3 Multi-Input Wake-Up
CONFIGURATION
Register
FIGURE 5. LLP Package Bottom View
0
0
1
1
Register
DATA
0
1
0
1
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
(Continued)
Port Set-Up
20047520
14
C2 Multi-Input Wake-Up
C1 Multi-Input Wake-Up
C0 Multi-Input Wake-Up
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All G
pins have Schmitt Triggers on their inputs. Pin G1 serves as
the dedicated WATCHDOG output with weak pull-up if
the WATCHDOG feature is selected by the Option regis-
ter. The pin is a general purpose I/O, if WATCHDOG
feature is not selected. If WATCHDOG feature is selected,
bit 1 of the Port G configuration and data register does not
have any effect on Pin G1 setup. Pin G7 is either input or
output depending on the oscillator option selected. With the
crystal oscillator option selected, G7 serves as the dedicated
output pin for the CKO clock output. With the internal R/C or
the external oscillator option selected, G7 serves as a gen-
eral purpose Hi-Z input pin and is also used to bring the
device out of HALT mode with a low to high transition on G7.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R/C or external clock option), the associated bits in the
data and configuration registers for G6 and G7 are used for
special purpose functions as outlined below. Reading the G6
and G7 data bits will return zeros.
The device will be placed in the HALT mode by writing a “1”
to bit 7 of the Port G Data Register. Similarly the device will
be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
Port G has the following alternate features:
G7 CKO Oscillator dedicated output or general purpose
G6 SI (MICROWIRE/PLUS Serial Data Input)
G5 SK (MICROWIRE/PLUS Serial Clock)
G4 SO (MICROWIRE/PLUS Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-
G0 INTR (External Interrupt Input)
G0 through G3 are also used for In-System Emulation.
Port J is an 8-bit I/O port. All J pins have Schmitt triggers on
the inputs. At RESET, Port J outputs are enabled and are
forced to the High state.
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
Pins L0 (SDA), L1 (SCL) and L2 inputs provide compatibility
with 1.8V logic levels when LVCMP (Option Register bit 7) is
set and the ACCESS.Bus is enabled.
Port L supports the Multi-Input Wake-Up feature on all eight
pins. Port L has the following alternate pin functions:
L7 Multi-Input Wake-Up
L6 Multi-Input Wake-Up
input.
DOG enabled, otherwise it is a general purpose I/O
G7
G6
CLKDLY
Alternate SK
Config. Reg.
HALT
IDLE
Data Reg.