cop8tab9 National Semiconductor Corporation, cop8tab9 Datasheet - Page 29

• Manufacturer Part Number: cop8tab9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

13.0 Power Save Modes
second method is with a low to high transition on the CKO
(G7) pin. This method precludes the use of the crystal clock
configuration (since CKO becomes a dedicated output), and
so may only be used with an R/C clock configuration. The
third method of exiting the HALT mode is by pulling the
RESET pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Multi-Input Wake-Up signal is not allowed to
start the chip running immediately since crystal oscillators
and ceramic resonators have a delayed start up time to
reach full amplitude and frequency stability. The IDLE timer
is used to generate a fixed delay to ensure that the oscillator
has indeed stabilized before allowing instruction execution.
In this case, upon detecting a valid Multi-Input Wake-Up
signal, only the oscillator circuitry is enabled. The IDLE timer
is loaded with a value of 256 and is clocked with the t
instruction cycle clock. The t
oscillator clock down by a factor of 10. The Schmitt trigger
following the CKI inverter on the chip ensures that the IDLE
timer is clocked only when the oscillator has a sufficiently
large amplitude to meet the Schmitt trigger specifications.
This Schmitt trigger is not part of the oscillator closed loop.
The start-up time-out from the IDLE timer enables the clock
signals to be routed to the rest of the chip.
13.2 IDLE MODE
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activities, except the
associated on-board oscillator circuitry and the IDLE Timer
T0, are stopped.
As with the HALT mode, the device can be returned to
normal operation with a reset, or with a Multi-Input Wake-Up
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the twelfth bit
(representing 4.096 ms at internal clock frequency of
10 MHz, t
This toggle condition of the twelfth bit of the IDLE Timer T0 is
latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the twelfth bit of the IDLE Timer T0. The interrupt can be
enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
C
= 1 µs) of the IDLE Timer toggles.
C
clock is derived by dividing the
FIGURE 22. Multi-Input Wake-Up from HALT
(Continued)
C
29
If an R/C clock option is being used, the fixed delay is
introduced optionally. A control bit, CLKDLY, mapped as
configuration bit G7, controls whether the delay is to be
introduced or not. The delay is included if CLKDLY is set,
and excluded if CLKDLY is reset. The CLKDLY bit is cleared
on reset.
The device has two options associated with the HALT mode.
The first option enables the HALT mode feature, while the
second option disables the HALT mode selected through bit
0 of the Option Byte. With the HALT mode enable option, the
device will enter and exit the HALT mode as described
above. With the HALT disable option, the device cannot be
placed in the HALT mode (writing a “1” to the HALT flag will
have no effect, the HALT flag will remain “0”).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
If the device is placed in the HALT mode, with the R/C
oscillator selected, the clock input pin (CKI) is forced to a
logic high internally. With the crystal or external oscillator the
CKI pin is TRI-STATE.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the “Enter Idle
Mode” instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the “Enter IDLE Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
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