cop8tab9 National Semiconductor Corporation, cop8tab9 Datasheet - Page 34

• Manufacturer Part Number: cop8tab9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

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14.0 Interrupts
Note 7: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last
address of a block. In this case, the table must be in the next block.
14.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc....) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If no active interrupt
is pending, than E0 is generated. This number replaces the
lower byte of the PC. The upper byte of the PC remains
unchanged. The new PC is therefore pointing to the vector of
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Arbitration Ranking
(Continued)
Software
Reserved for NMI
External
Timer T0
Timer T1
Timer T1
MICROWIRE/PLUS
ACCESS.Bus
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Port L/Wake-up
Port C/Wake-up
Default VIS
Source Description
TABLE 14. Interrupt Vector Table
INTR Instruction
G0
Underflow
T1A/Underflow
T1B
BUSY Low
Address Match, Bus Error,
Negative Acknowledge,
Valid Sto or SDAST is set
Port L Edge
Port C Edge
Reserved
34
the active interrupt with the highest arbitration ranking. This
vector is read from program memory and placed into the PC
which is now pointed to the 1st instruction of the service
routine of the active interrupt with the highest arbitration
ranking.
Figure 26 illustrates the different steps performed by the VIS
instruction. Figure 27 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
0yFE–0yFF
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
0yF6–0yF7
0yF4–0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0yEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
Vector Address (Note 7)
(Hi-Low Byte)