cop8tab9 National Semiconductor Corporation, cop8tab9 Datasheet - Page 25

• Manufacturer Part Number: cop8tab9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

12.0 Timers
The device contains a very versatile set of timers (T0 and
T1). Timer T1 and associated autoreload/capture registers
power up containing random data.
12.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE Timer T0, which is a
16-bit timer. The user cannot read or write to the IDLE Timer
T0, which is a count down timer.
The clock to the IDLE Timer is the instruction cycle clock
(one-tenth of the CKI frequency).
In addition to its time base function, the Timer T0 supports
the following functions:
Figure 18 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
The ITSEL bits of the ITMR register are cleared on Reset
and the Idle Timer period is reset to 4,096 instruction cycles.
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
• Start up delay from POR
ITSEL2
0
0
0
0
1
1
1
1
TABLE 13. Idle Timer Window Length
ITSEL1
0
0
1
1
0
0
1
1
ITSEL0
0
1
0
1
0
1
0
1
FIGURE 18. Functional Block Diagram for Idle Timer T0
Reserved - Undefined
Reserved - Undefined
Reserved - Undefined
16,384 inst. cycles
32,768 inst. cycles
65,536 inst. cycles
Idle Timer Period
4,096 inst. cycles
8,192 inst. cycles
25
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k selected
clocks), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer
interrupt enable bit T0EN must be set, and the GIE (Global
Interrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to Section 13.2
IDLE MODE.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bit 3 of the ITMR Register is reserved and should
not be used as a software flag. Bits 4 through 7 of the ITMR
Register are reserved and must be zero.
12.1.1 ITMR Register
RSVD: These bits are reserved and must be set to 0.
ITSEL2:0: Selects the Idle Timer period as described in
Table 13
Any time the IDLE Timer period is changed there is the
possibility of generating a spurious IDLE Timer interrupt by
setting the T0PND bit. The user is advised to disable IDLE
Timer interrupts prior to changing the value of the ITSEL bits
of the ITMR Register and then clear the T0PND bit before
attempting to synchronize operation to the IDLE Timer.
Bit 7
Bit 6
RSVD
Bit 5
Bit 4
20047530
Bit 3
ITSEL2 ITSEL1 ITSEL0
Bit 2
Bit 1
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Bit 0