cop8tab9 National Semiconductor Corporation, cop8tab9 Datasheet - Page 42

• Manufacturer Part Number: cop8tab9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
16.0 MICROWIRE/PLUS
17.0 ACCESS.Bus Interface
The ACCESS.Bus interface module (ACB) is a two-wire
serial interface compatible with the ACCESS.Bus physical
layer. It permits easy interfacing to a wide range of low-cost
memories and I/O devices, including: EEPROMs, SRAMs,
timers, A/D converters, D/A converters, clock chips, and
peripheral drivers. It is compatible with Intel’s SMBus and
Philips’ I
master or slave, and can maintain bidirectional communica-
tions with both multiple master and multiple slave devices.
The ACCESS.Bus protocol uses a two-wire interface for
bidirectional communication between the devices connected
to the bus. The two interface signals are the Serial Data Line
(SDA) and the Serial Clock Line (SCL). These signals should
be connected to the positive supply, through pull-up resis-
tors, to keep the signals high when the bus is idle. When the
ACCESS.Bus module is enabled and Bit 7 of the Option
Register (LVCMP) is set, the SDA and SCL inputs, along with
input L2, provide compatibility with 1.8V logic levels.
Each data transaction is composed of a Start Condition, a
number of byte transfers (programmed by software) and a
• ACCESS.Bus master and slave
• Supports polling and interrupt-controlled operation
• Generate a wake-up signal on detection of a Start Con-
• Optional internal pull-up on SDA and SCL pins
• Optional 1.8V logic compatibility on SDA and SCL pins
dition, while in reduced-power mode
FIGURE 32. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High
2
C bus. The module can be configured as a bus
(Continued)
FIGURE 33. Bit Transfer
42
The ACCESS.Bus protocol supports multiple master and
slave transmitters and receivers. Each bus device has a
unique address and can operate as a transmitter or a re-
ceiver (though some peripherals are only receivers).
17.1 DATA TRANSACTIONS
During data transactions, the master device initiates the
transaction, generates the clock signal and terminates the
transaction. For example, when the ACB initiates a data
transaction with an ACCESS.Bus peripheral, the ACB be-
comes the master. When the peripheral responds and trans-
mits data to the ACB, their master/slave (data transaction
initiator and clock generator) relationship is unchanged,
even though their transmitter/receiver functions are re-
versed.
One data bit is transferred during each clock period. Data is
sampled during the high phase of the serial clock (SCL).
Consequently, throughout the clock high phase, the data
must remain stable (see Figure 33 ). Any change on the SDA
signal during the high phase of the SCL clock and in the
middle of a transaction aborts the current transaction. New
data must be driven during the low phase of the SCL clock.
This protocol permits a single data line to transfer both
command/control information and data using the synchro-
nous serial clock.
Stop Condition to terminate the transaction. Each byte is
transferred with the most significant bit first, and after each
byte, an Acknowledge signal must follow.
20047579
20047541