x4c105 Intersil Corporation, x4c105 Datasheet - Page 6

• Manufacturer Part Number: x4c105
• Description: Cpu Supervisor With Novram And Output Ports
• Manufacturer: Intersil Corporation

The master terminates the data byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 7 for the address,
acknowledge, and data transfer sequence.
Figure 7. Page Write Operation
Signals from
Signals from
the Master
the Slave
SDA Bus
6
S
a
r
t
t
Address
Slave
0
A
C
K
Address
X4C105
Byte
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be affected.
A
C
K
Data
(1)
(1 < n < 16)
A
C
K
Data
(n)
A
C
K
S
o
p
t
March 18, 2005
FN8124.0