x4c105 Intersil Corporation, x4c105 Datasheet - Page 9

• Manufacturer Part Number: x4c105
• Description: Cpu Supervisor With Novram And Output Ports
• Manufacturer: Intersil Corporation

Figure 11. Sequential Read Sequence
After loading the entire slave address byte from the
SDA bus, the device compares the device select bits
with the status of the device select pins. Upon a cor-
rect compare, the device outputs an acknowledge on
the SDA line.
Slave Byte
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
1
Signals from
Signals from
the Master
the Slave
SDA Bus
0
1
0
Address
Slave
9
S2
1
C
A
K
S1
Data
(1)
A8
R/W
A
C
K
X4C105
Data
(2)
Write Protect Operations
The WP pin provides write protection. The WP pin pro-
tects the upper half of the array.
Table 1. Write Protected Areas
WP Pin
HIGH
LOW
A
C
K
(n is any integer greater than 1)
Writes possible to all locations
No writes to 100H-1FFH, writes possible
to 000H to 0FFH
Data
(n-1)
Serial Memory Write Protection
C
A
K
Data
(n)
March 18, 2005
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FN8124.0