xr16m698 Exar Corporation, xr16m698 Datasheet - Page 15

• Manufacturer Part Number: xr16m698
• Description: 1.62v To 3.63v High Performance Octal Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
.
Automatic RTS/DTR flow control is used to prevent data overrun to the local receiver FIFO. The RTS#/DTR#
output pin is used to request remote unit to suspend/resume data transmission. The flow control features are
individually selected to fit specific application requirement (see
•
•
•
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (HIGH) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level (
trigger level below the programmed trigger level.
However, even under these conditions, the 698 will continue to accept data until the receive FIFO is full if the
remote UART transmitter continues to send data.
•
2.10
Select RTS (and CTS) or DTR (and DSR) through MCR bit-2.
Enable auto RTS/DTR flow control using EFR bit-6.
The auto RTS or auto DTR function must be started by asserting the RTS# or DTR# output pin (MCR bit-1 or
bit-0 to a logic 1, respectively) after it is enabled.
If used, enable RTS/DTR interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR bit-5 will be set to 1.
See Table 15
Auto RTS/DTR Hardware Flow Control Operation
T
ABLE
CH0 0x00 Read RHR
CH2 0x20 Read RHR
CH3 0x30 Write THR
CH3 0x30 Read RHR
CH4 0x40 Read RHR
CH0 0x00 Write THR
CH1 0x10 Write THR
CH1 0x10 Read RHR
CH2 0x20 Write THR
CH4 0x40 Write THR
CH5 0x50 Write THR
6: T
CH5 0x50 Read RHR
CH7 0x70 Read RHR
CH6 0x60 Read RHR
CH6 0x60 Write THR
CH7 0x70 Write THR
). The RTS# output pin will be asserted (LOW) again after the FIFO is unloaded to the next
RANSMIT AND
THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible)
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
R
ECEIVE
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
H
OLDING
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
15
R
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
EGISTER
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Figure 9
L
OCATIONS
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
):
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
, 16C550
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
COMPATIBLE
THRRHR1
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
XR16M698