xr16m698 Exar Corporation, xr16m698 Datasheet - Page 27

• Manufacturer Part Number: xr16m698
• Description: 1.62v To 3.63v High Performance Octal Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
The 698 includes a 16-bit general purpose timer/counter. Its clock source may be selected from internal crystal
oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or re-
triggerable for a periodic signal. An interrupt may be generated when the timer times out and will show up as a
Channel 0 interrupt (see
TIMELSB, TIMERMSB]. These registers provide start/stop and re-triggerable or one-shot operation (see
Table 11
alarm.
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit-0 of the
TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Default value is zero (timer disabled) upon powerup and reset.
The bits 3:0 of this register are used to issue commands. The commands are self-clearing, so reading this
register does not show the last written command. Reading this register returns a value of 0x01 when there is a
Timer interrupt pending and 0x00 at all other times.
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
P
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10
RIORITY
1
2
3
4
5
6
7
x
below). The time-out output of the Timer can be set to generate an interrupt for system or event
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (
0
Bit
X
2
0
0
0
0
1
1
1
1
XX-XX-00-00)
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMER [7:0] Reserved
TIMERCNTL [7:0] Register
Bit
T
1
0
0
1
1
0
0
1
1
ABLE
TIMERMSB Register
Bit
0
0 None or wake-up indicator
1 RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
0 RXRDY Time-out: Cleared same way as RXRDY INT.
1 TXRDY, THR or TSR (auto RS-485 mode) empty, clears after reading ISR register.
0 MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
1 Reserved.
0 Reserved.
1 TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
10: UART C
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
clears after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR
register.
Reserved in other channels.
Table 10
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
16-Bit Timer/Counter Programmable Registers
). It is controlled through 4 configuration registers [TIMERCNTL, TIMER,
HANNEL
Bit-9 Bit-8
[7:0] I
NTERRUPT
I
NTERRUPT
27
Bit-7
S
S
OURCE
OURCE
Bit-6
(
S
E
)
NCODING AND
AND
Bit-5
TIMERLSB Register
C
LEARING
Bit-4
C
Bit-3
LEARING
Bit-2
XR16M698
Bit-1 Bit-0
DEFAULT