xr16m698 Exar Corporation, xr16m698 Datasheet - Page 30

• Manufacturer Part Number: xr16m698
• Description: 1.62v To 3.63v High Performance Octal Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16M698
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need.
Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that
channel will be reset to the default condition, see
channel 0 with bit-7=1 resets channel 7.
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power
consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when there is
no interrupt pending. When all 8 UARTs are put to sleep, the on-chip oscillator shuts off to further conserve
power. In this case, the octal UART is awaken by any of the UART channels from a receive data byte or a
change on any of the modem inputs (CTS#, DSR#, CD#, RI#). The UART is ready after 32 crystal clocks to
ensure full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Logic 0
(default) and logic 1 disable and enable sleep mode respectively.
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8-
bit content in the DVID register provides device identification. A return value of 0x68 from this register indicates
the device is a XR16M698. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02 for revision B
and so on. This information is very useful to the software driver for identifying which device it is communicating
with and to keep up with revision changes.
Device identification for the type of UART. The Device ID for the M698 is 0x68.
Revision number of the XR16M698. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB[0]: Simultaneous write to all 8 UARTs
•
•
REGB[7:1]: Reserved.
3.1.5
3.1.6
3.1.7
3.1.7.1
3.1.7.2
3.1.8
Logic 0 = Write to each UART configuration register individually (default).
Logic 1 = Enable simultaneous write to all 8 UART configuration registers. This can be very useful during
device initialization in the power-up and reset routines.
RESET [7:0] (default 0x00)
SLEEP [7:0] (default 0x00)
Device Identification and Revision
REGB [7:0] (default 0x00)
DVID [7:0] (default 0x68)
DREV [7:0] (default (0x01)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7
Ch-7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Individual UART Channel Sleep Enable
Individual UART Channel Reset Enable
Ch-6
Ch-6
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
SLEEP Register
RESET Register
Table 19
30
for details. As an example, bit-0 =1 resets UART
REV. 1.0.0