xr16m698 Exar Corporation, xr16m698 Datasheet - Page 37

• Manufacturer Part Number: xr16m698
• Description: 1.62v To 3.63v High Performance Octal Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software compatibility.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
•
•
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
•
•
FCR[0]: TX and RX FIFO Enable
•
•
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
4.6
Logic 0 = Set DMA to mode 0 (default).
Logic 1 = Set DMA to mode 1.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
Line Control Register (LCR) - Read/Write
B
FCR
IT
0
0
1
1
-7
T
ABLE
B
FCR
IT
0
1
0
1
15: T
-6
RANSMIT AND
B
FCR
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
IT
0
0
1
1
-5
BIT
FCR
0
1
0
1
R
-4
ECEIVE
R
ECEIVE
FIFO T
L
EVEL
16
24
28
37
8
T
RIGGER
RIGGER
Table 15
T
T
RIGGER
ABLE AND
T
RANSMIT
16
24
30
8
below shows the selections.
L
EVEL
L
EVEL
16C650A, 16L651
S
C
ELECTION
OMPATIBILITY
XR16M698