xr16m698 Exar Corporation, xr16m698 Datasheet - Page 36

• Manufacturer Part Number: xr16m698
• Description: 1.62v To 3.63v High Performance Octal Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16M698
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
]
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from LOW to HIGH.
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. Reading the
XCHAR register will indicate which character (Xoff or Xon) was received last. If it is a special character
interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is received.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
4.4.1, Interrupt Generation:” on page 35
ISR[0]: Interrupt Status
•
•
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
4.5
P
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
RIORITY
L
EVEL
X
1
2
3
4
5
6
7
FIFO Control Register (FCR) - Write Only
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
T
EGISTER
IT
0
0
1
0
0
0
0
0
ABLE
-3
14: I
B
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
and
B
B
ITS
IT
“Section 4.4.2, Interrupt Clearing:” on page 35
1
0
0
1
0
0
0
0
-1
S
OURCE AND
36
B
IT
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default) or wake-up indicator
P
RIORITY
Table 15
L
S
EVEL
OURCE OF THE INTERRUPT
shows the complete selections.
Table 14
). See
for details.
REV. 1.0.0
“Section