hsp50210 Intersil Corporation, hsp50210 Datasheet
hsp50210
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hsp50210 Summary of contents
Page 1
... AGC and Carrier Tracking Loops. The PLL system solution is completed by the HSP50210 error detectors and second order Loop Filters that provide carrier tracking and symbol synchronization signals. In ...
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... QIN2 28 QIN1 29 QIN0 30 SOFSYNC 31 32 SOF Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HSP50210JC- Lead PLCC HSP50210JI-52 - Lead PLCC 3-2 HSP50210 84 LEAD PLCC TOP VIEW PKG ...
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... O Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The clock is programmable and has a 50% duty cycle. Note: Not used when the HSP50110 is used with the HSP50210 (see Table 41). ISER I In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB first and is synchronous to SERCLK (see Input Controller Section) ...
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... SERCLK X ISER QSER NCO SOFSYNC SOF SERIAL COFSYNC OUTPUT COF FORMATTER SLOCLK 8 C7-0 WR MICROPROCESSOR INTERFACE RD A2-0 CLK FRZ_ST FRZ_CT FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50210 AGC GAIN ERROR LOOP FILTER DETECT MATCHED FILTERING M I&D RRC RRC I& ...
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... HSP50110 providing the coarse AGC, and the HSP50210 providing the fine or final AGC. A top level block diagram of the HSP50210 is shown in Figure 1. This diagram shows the major blocks and the multiplexers used to reconfigure the data path for various architectures ...
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REGISTER ENABLE RATE @ = SYNC RATE = TWICE SYMBOL RATE * ! = SYMBOL RATE BLANK = CLK RATE MATCHED FILTERING HI/LO REG NCO MIXER REG BYPASS MIXER BYPASS RRC ...
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... Carrier Tracking Loop Filter to the same value and zeroing the lead gain. Matched Filtering The HSP50210 provides two selectable matched filters: a Root Raised Cosine Filter (RRC) and an Integrate and Dump (I&D) filter. These are shown in Figure 3. The RRC fi ...
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... CLK CLK CLK CLK FREQUENCY (NORMALIZED TO INPUT SAMPLE RATE) FIGURE 5. PASSBAND RIPPLE OF RRC FILTER IN HSP50210 3-8 HSP50210 TABLE 1. ROOT RAISED COSINE COEFFICIENTS COEFFICIENT INDEX 4f f CLK CLK 10 2 The I&D filter consists of an accumulator, a programmable shifter and a two sample summer as shown in Figure 3. The programmable shifter is provided to compensate for the gain introduced by the accumulator (see Table 14) ...
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... Cartesian to Polar Coordinate Converter. This filter may be the Integrate and Dump filter shown in Figure 8, the RRC filter upstream in the HSP50210 data path, or some other filter outside the DCL chip. The magnitude signal usually /2 ...
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... For the HSP50210, the AGC Loop Gain provides for a variable attenuation of the input to the loop filter. The AGC gain mantissa is a 4-bit value which provides error signal scaling from 0 ...
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... Table 4, while Table 5 details the decimal value for the 4 exponent values FIGURE 8. AGC 3-11 HSP50210 AGC LOOP AGC LOOP GAIN GAIN EXPONENT † MANTISSA † -7 -14 (0.000 TO 0.9375 ...
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... Figure 9. The upper and lower limits 0.703125 have the same value for this case. 0.718750 The HSP50210 provides two mechanisms for monitoring 0.734375 signal strength. The first, which involved the THRESH 0.750000 signal, has already been described. The second mechanism is via the Microprocessor Interface ...
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... MIN Thus, the expected range for the AGC rate is approximately 0.0004 to 0.0469dB/symbol time. 3-13 HSP50210 only exponent terms of the various gains will be sufficient to yield a rough order of magnitude of the range of the AGC Loop response. The results are shaded in the last column of Table 6 and provided in detail in Equations 9A and 9B. ...
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... The main signal path, with processing block gains and path bit weightings, is shown in Figure 10. The quadrature inputs to the HSP50210 are 10-bit fractional two’s complement numbers with relative bit weightings, as shown in the Figure 10. The first element in the processing chain is the Mixer, which scales the quadrature outputs of the complex multiplier by 1/2 providing a gain ...
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REGISTER ENABLE RATE ! = SYMBOL RATE BLANK = CLK RATE R FRZ_ST E G SAMPLING ERROR DETECTOR ‘0’ TRANSITION MUX DETECT I DATA END DECISION TRANSITION MID-POINT - I + MID MID-SYMBOL ‘0’ ! TRANSITION MUX DETECT Q DATA ...
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... SOF output, to the NCO/VCO controlling the baseband sample rate (see Serial Output Section). In basic configurations, the SOF output of the HSP50210 is connected to the SOF input of the HSP50110. Two sets of registers are provided to store the loop gain parameters associated with acquisition and tracking ...
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... The I and Q inputs to the slicer are encoded into 3-bit soft decisions ISOFT(2-0) and QSOFT(3-0). These signals are routed to the OUTA(9-4) outputs by the Output Configuration Control Register Selector bits 0-3 (see Table 42). 3-17 HSP50210 ‘0’ STRONGER PROBABILITY DENSITY FUNCTION + ...
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... CLK Serial Output Section). In applications where the carrier tracking is performed using the NCO on board the HSP50210, the loop filter output is fed to the on-board NCO as a frequency control. The gain for the lead and lag paths of the Carrier Loop Filter are set through a programmable mantissa and exponent. ...
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FRZ_CT CARRIER PHASE ERROR DETECT PHASE OFFSET + SHIFT SHIFT LEFT REG “0” PHASE ERROR ( ) E INVERT DELAY PHASE @ * OR ( 16) ERROR - + DISCRIMINATOR “0” + FREQUENCY ...
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... HSP50210 BITS MULT KEPT OUT (RND) SHIFT = (12) (12 (11) (11 (10) (10 (9) ( (8) (8) 11. 12 ...
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... NOTE: - FLB 0.075Hz/Baud = 12Kbps. min clk 3-21 HSP50210 SHIFT = 0 SHIFT = 32 SHIFT COUNTS (8) - shift28 7. - shift27 6 - shift26 5 - shift25 4 - shift24 3 - shift23 2 - shift22 1 - shift21 0 - shift20 - shift19 - shift18 - shift17 - shift16 - shift15 - shift14 - shift13 - shift12 ...
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... Phase 3-22 HSP50210 Error Detector. For PSK demodulation, this block is bypassed by setting the offset and shift terms to zero (see Frequency Error Detector Control Register; Table 19). The frequency error term may be selected for output via the Output Select Block ...
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... BPSK, <22.5 (typical after shift); and Integration Count = Integration Period measured in symbol times. 3-23 HSP50210 The False Lock Detector is used to indicate false lock on square wave data in a high SNR environment. A false lock condition is detected by monitoring the final integration stage in the Q branch of the Integrate and Dump Filter (see Figure 3) ...
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... TC START TC SWEPT 3-24 HSP50210 are monitored by an external processor to determine when lock has been achieved. In this mode the accumulator pre- loads are typically set to zero and the accumulator output is compared in the processor against a threshold equal to the maximum Phase Error per sample times the number of samples per Integration Period ...
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... In applications where the HSP50210 is used with the HSP50110, both parts must be supplied with the same CLK and the HSP50210 is configured to use CLK as the serial clock. The serial output can be configured for word containing from bits. ...
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... Microprocessor Interface. Writing to the Microprocessor Interface The HSP50210 is configured for operation by loading a set of thirty-two control registers which range in size from bits. They are loaded by first writing the configuration data to the Microprocessor interface’s four holding registers and then writing the target address to the Write Address Register as shown in Figure 19 ...
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... Table 12. The contents of the output holding registers are multiplexed out a byte at a time on C7-0 by changing A2-0 and asserting RD (see Read/Write Address Map in Table 11). 3-27 HSP50210 TABLE 12. READ ENABLE ADDRESS MAP ADDRESS HOLDING REGISTER ENABLE 0 Carrier Loop Filter Lag Accumulator. Enables output of holding register containing 32 MSBs of the lag accumulator ...
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... Select the MSByte of the output holding register for output. 4 Assert RD low to output data on C0-7. (Must wait for 6 CLKs after loading the holding registers). 5 Select other bytes of holding register by changing A0-2 and asserting RD. FIGURE 22. LOOP FILTER ACCUMULATOR READ SEQUENCE 3-28 HSP50210 2 3 EARLIEST TIME ANOTHER FIGURE 21. CONTROL REGISTER LOADING SEQUENCE DON’T CARE 3 ...
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... Symbol Tracking Loop Filter Lag Accumulator Load Complete. This bit is used to determine when a 32-bit load of Symbol Track Lag Accumulator is complete. The accumulator load is initialized by loading the Write Address Register with 19 (decimal) as described in Table 33 Load not complete Load complete. 3-29 HSP50210 MSW LSW ...
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... Load Write Address Register with 30 dec mode). 9 Keep Address Restart the Lock Detector. 10 Load Write Address Register with 25 dec FIGURE 24. PROCESSOR INTERRUPT MONITOR/LOCK DETECTOR READ . CLK A0-2 C7-0 3-30 HSP50210 MSW LSW enable the Lock Detector Phase Error Accumulator for Reading. ...
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... Decimation by 16 (accumulate 8 samples, sample pair summing). 0100 = Decimation by 32 (accumulate 16 samples, sample pair summing). All other codes are invalid. 0 OQPSK Data 0 = Disables Q channel data delay. De-Skew Select 1 = Delays Q Channel by 1/2 Symbol time to remove OQPSK stagger. 3-31 HSP50210 DESTINATION ADDRESS = 0 DESCRIPTION ...
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... AGC upper and lower limits to the same value, the AGC can be set to a fixed gain. TABLE 17. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER BIT POSITION FUNCTION 31-8 Not Used No programming required. 7-6 Reserved Reserved. Set to 0 for proper operation. 3-32 HSP50210 DESTINATION ADDRESS = 1 DESCRIPTION - ...
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... Reserved. Set to 0 for proper operation. 6 Lead/Lag to Serial 0 = The Carrier Loop Filter’s Lag Accumulator is routed to the Serial Output Controller. Output Routing 1 = The lead and lag paths in the Carrier Loop Filter are summed and routed to the Serial Output 3-33 HSP50210 DESTINATION ADDRESS = 3 DESCRIPTION -3. ...
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... Loop Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit, the upper 32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero. 3-34 HSP50210 DESTINATION ADDRESS = 6 DESCRIPTION DESTINATION ADDRESS = 7 ...
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... Sets Frequency Error Gain. Format same as lead gain mantissa (see Table 24). Bit position 11 is the (Acquisition) MSB. 13-9 AFC Gain Exponent Sets Frequency Error Gain. Format same as lead gain exponent (see Table 24). Bit position 4 is the MSB. (Acquisition) 3-35 HSP50210 DESTINATION ADDRESS = 10 DESCRIPTION - -4. 2 ...
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... The threshold levels are determined by equally dividing up the signal range by the order of the signal. For example, a 2ary signal would divide the signal would have thresholds at: -0.5, 0, and +0.5. 3-36 HSP50210 DESTINATION ADDRESS = 12 DESCRIPTION DESTINATION ADDRESS = 13 DESCRIPTION DESTINATION ADDRESS = 14 DESCRIPTION ~ 1 ...
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... These bits are the 4 fractional bits of the lead gain mantissa shown below: Lead Gain Mantissa Symbol Tracking Lead Gain Mantissa = 01. 2 (Acquisition) This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary. Bit position 17 is the MSB. 3-37 HSP50210 DESTINATION ADDRESS = 14 DESCRIPTION DESTINATION ADDRESS = 15 DESCRIPTION DESTINATION ADDRESS = 16 DESCRIPTION ...
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... Table 13 in the Microprocessor Interface Section). The contents of the holding registers are loaded into the 32 MSBs of the lag accumulator and the 8 LSBs are zeroed good practice to load the LAG accumulators at the very end of a configuration load sequence. 3-38 HSP50210 DESTINATION ADDRESS = 17 DESCRIPTION -(32-E), -32 ...
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... The accumulator roll over is at the 2 15-0 False Lock See above. The Lock Detector State Machine only uses the accumulator during the verify state during Accumulator which the Track parameters are used. Pre-Load (Track) 3-39 HSP50210 DESTINATION ADDRESS = 20 DESCRIPTION DESTINATION ADDRESS = 21 DESCRIPTION BIT WEIGHTING OF ACCUMULATOR PRE-LOAD 10 9 ...
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... Set to zero for proper operation. 0 Microprocessor This bit is used to enable the output of the Frequency Sweep Block to the lag path of the Symbol Tracking Frequency Sweep Loop Filter. This bit is only used under microprocessor control of the Lock Detector. Enable 3-40 HSP50210 DESTINATION ADDRESS = 23 DESCRIPTION ...
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... COFSYNC pulses “High” one serial clock before data word on COF. Polarity 1 = COFSYNC pulses “Low” one serial clock before data word on COF. (COF output) Set to 0 for use with the HSP50110. 3-41 HSP50210 DESTINATION ADDRESS = 24 DESCRIPTION DESTINATION ADDRESS = 25 DESCRIPTION DESTINATION ADDRESS = 26 ...
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... CLK is used as the serial clock. COF Output 1 = SLOCLK is used as the serial clock. Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial clock for the SOF and COF outputs, and the same CLK must be used by both chips. 6-4 Serial Word Length for ...
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... MAG(7:0) and PHASE(7:0) These signals are useful in signal detection applications, where presence of a signal is represented by a particular signal magnitude or phase. 3-43 HSP50210 DESTINATION ADDRESS = 28 DESCRIPTION by CW26 bit 7, with one sign bit (ISOFT2) and two soft decision bits. by CW26 bit 7, with one sign bit (QSOFT2) and two soft decision bits. ...
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... Filter Lag Accumulator, Symbol Tracking Loop Filter Lag Accumulator, and the AGC Accumulator. The Microprocessor Read sampled accumulator values are loaded into the output holding registers for reading via the Microprocessor Interface. Allow 6 CLKs until the output holding register is stable for reading. 3-44 HSP50210 DESTINATION ADDRESS = 28 DESCRIPTION TABLE 42A. AOUT BIT DEFINITIONS AOUT 6 ...
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... This bit pulses “High” for one CLK synchronous with a new signal output on OUTB6-0 (see Output Selector Control Register: Table 45). For example if the lower 4 bits of the Output Selector Register are set to 0010 (BINARY), This bit will pulse active on the same CLK that new FE7-1 data is output. 3-45 HSP50210 DESTINATION ADDRESS = 30 DESCRIPTION DESTINATION ADDRESS = 31 DESCRIPTION TABLE 46 ...
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... NOTE: 6. Noise Bandwidth of RRC Filter is 0.492676. 3-46 HSP50210 and without the root raised cosine filter in the HSP50210. The noise bandwidth is measured relative to the output sample rate. TABLE A INT/DUMP INT/DUMP W/COMP 3RD AND RRC AND RRC ORDER CIC ...
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... Setup Time IIN9-0, QIN9-0, SYNC, FZ_CT, FZ_ST to CLK Hold Time IIN9-0, QIN9-0, SYNC, FZ_CT, FZ_ST FROM CLK Setup Time ISER, QSER, SSYNC to SERCLK 3-47 HSP50210 Thermal Information Thermal Resistance (Typical, Note 7) +0.5V PLCC Package ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 13. Set up time required to ensure action initiated SERCLK will be seen by a particular CLK. AC Test Load Circuit SWITCH S1 OPEN FOR I † Test head capacitance. 3-48 HSP50210 5.0V 5 (Commercial ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 3-49 HSP50210 t WRH t ...