hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 36

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

POSITION
POSITION
POSITION
31-16
15-13
12-11
10-9
BIT
BIT
BIT
N/A
8-5
4-0
Not Used
Reserved
Sampling Error Shift
Factor
Modulation Order
Select
AFC Gain Mantissa
(Track)
AFC Gain Exponent
(Track)
Carrier Lag
Accumulator
Initialization
FUNCTION
FUNCTION
FUNCTION
TABLE 27. CARRIER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER
3-36
TABLE 26. FREQUENCY SWEEP/ AFC LOOP CONTROL REGISTER (Continued)
TABLE 28. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER
No programming required.
Reserved. Set to 0 for proper operation.
The sampling error shifter is provided to left shift the sampling error to full scale before input to the Symbol
Tracking Loop Filter. The magnitude of the sampling error varies with the number of symbol decision levels,
and a left shift of 1 to 4 places is provided as required by modulation order. Suggested settings are provided
below:
00 = x2 2 levels on each rail (BPSK, QPSK).
01 = x4 4 levels on each rail (8 PSK).
10 = x8 8 levels on each rail.
11 = x16 16 levels on each rail.
Note: Saturation is provided in case of overflow.
These bits set the threshold levels used by the symbol decision blocks in the Sampling Error detector. The
end-symbol samples on either the I or Q processing path are compared against the selected threshold set
to determine the expected symbol value used in calculating the transition midpoint. The threshold levels
can be set for up to 16ary signals on both the I and Q processing path. The decision thresholds are set as
given below.
00 = 2ary signal (Use this setting for BPSK, QPSK, and OQPSK signals).
01 = 4ary signal.
10 = 8ary signal.
11 = 16ary signal.
The threshold levels are determined by equally dividing up the signal range by the order of the signal. For
example, a 2ary signal would divide the
signal would have thresholds at:
-0.5, 0, and +0.5.
Sets Frequency Error Gain. Format same as lead gain mantissa (see Table 24). Bit position 11 is the
MSB.
Sets Frequency Error Gain. Format same as lead gain exponent (see Table 24). Bit position 4 is the MSB.
Writing this address initializes the lag accumulator with the contents of the 4 Microprocessor Interface
Holding Registers at the start of the next Carrier Loop Filter Computation cycle. The contents of the hold-
ing registers should not be changed until after the start of a new compute cycle, since the current contents
of the holding registers are loaded at the compute cycle start. The Microprocessor Interface can be used
to read an Internal Status Register which signals when the lag accumulator load is complete (see Micro-
processor Interface Section). The contents of the holding registers are loaded into the 32 MSBs of the
lag accumulator and the 8 LSBs are zeroed.
It is good practice to load the LAG Accumulators at the very end of a configuration load sequence.
DESTINATION ADDRESS = 12
DESTINATION ADDRESS = 13
DESTINATION ADDRESS = 14
HSP50210
~
1.0 to -1.0 signal range by two forcing threshold at 0.0. A 4ary
DESCRIPTION
DESCRIPTION
DESCRIPTION