hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 9

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

The phase conversion is equivalent to:
where tan
conversion output is an 8-bit two’s complement output which
ranges from -1.0 to 0.9922 (80 to 7f HEX, respectively). The
-1 to almost 1 range of the phase output represents phase
values from - to , respectively. An example of the I/Q to
phase mapping is shown in Figure 6. The phase and
magnitude values may be output via the Output Selector bits
0-3 (see Table 42).
FIGURE 6C. CARTESIAN/POLAR CONVERTER PHASE OUTPUT
Phase (I, Q)
FIGURE 6B. Q INPUT TO CARTESIAN/POLAR CONVERTER
FIGURE 6A. I INPUT TO CARTESIAN/POLAR CONVERTER
-0.5
-1.0
-0.5
-1.0
-0.5
-1.0
1.0
0.5
1.0
0.5
1.0
0.5
0
0
0
-
-
-
-1
( ) is the arctangent function. The phase
=
tan
–
- /2
1
- /2
- /2
Q I ,
INPUT PHASE
INPUT PHASE
INPUT PHASE
3-9
0
0
0
/2
/2
/2
(EQ. 6)
HSP50210
The I/Q data path selected for input to the Cartesian to Polar
converter determines the input data rate of the AGC and
carrier tracking loops. If the I/Q data path out of the Integrate
and Dump Filter is selected, the AGC is fed with magnitude
values produced by the end-symbol samples. Magnitude
values produced by midsymbol samples are not used
because these samples occur on symbol transitions, resulting
in poor signal magnitude estimates. The Carrier Tracking
block is fed with phase values generated from both the end
and mid-symbol samples. The carrier tracking loop filter,
however, is only fed with Phase Error terms generated by the
end symbol samples. If the input of the I&D is selected for
input to the coordinate converter, the control loops are fed
with data at the I/Q data rate. The desired data path input to
the Cartesian to Polar converter is specified in the Data Path
Configuration Control Register, bit 8 (see Table 14).
AGC
The AGC loop operates on the main data path (I and Q) and
performs three signal level adjusting functions: 1)
maximizing dynamic range, 2) compensating for SNR
variations, and 3) maintaining an optimal level into the Soft
Decision Slicer. The AGC Loop Block Diagram, shown in
Figure 7, consists of an Error Detector, a Loop Filter, and
Signal Gain Adjusters (multipliers). The AGC Error Detector
generates an error signal by subtracting the programmable
AGC threshold from the magnitude output of the Cartesian
to Polar Converter. This difference signal is scaled (gain
adjusted via multiplier and shifter), then filtered (integrated)
by the AGC Loop Filter to generate the gain correction to the
I and Q signals at the multipliers. If a fixed gain is desired,
set the upper and lower limits equal.
The AGC responds to the magnitude of the sum of all the
signals in the bandpass of the narrowest filter preceding the
Cartesian to Polar Coordinate Converter. This filter may be
the Integrate and Dump filter shown in Figure 8, the RRC
filter upstream in the HSP50210 data path, or some other
filter outside the DCL chip. The magnitude signal usually
contains several components: 1) the signal of interest
component, 2) the noise component, and 3) interfering
signals component. At high SNR’s the signal of interest is
significantly greater than the other components. At lower
SNR’s, components 2 or 3 may become greater than the
signal of interest. Narrowing the filter bandwidth is the
primary technique used to mitigate magnitude contributions
of component 3. This will also improve the SNR by
reducing the magnitude contributions of element 2.
Consideration of the range of signal amplitudes expected
into the HSP50210, in conjunction with a gain distribution
analysis, will provide the necessary insight to set the signal
level into the Soft Decision Slicer to yield optimum
performance. Note: Failure to consider the variations
due to noise or interfering signals, can result in signal
limiting in the HSP50210 processing algorithms, which
will degrade the system Bit Error Rate performance.