hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 30

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
.
10
1
2
3
4
5
6
7
8
9
LKINT Asserts Indicating End of Lock Detector Accumulation Cycle; Accumulators Ready to Read.
Set A0-2 to 5 for Reading Lock Detector.
Load Read Address Register with 3
Set A0-2 to 3 for Phase Error (PE) Read.
Change Read Address to (2; 1; 0) to read various Lock Detection values.
Change Address to 4 to Initialize the Lock Detector.
Load Write Address Register with 30
Keep Address to 4 to Restart the Lock Detector.
Load Write Address Register with 25
mode).
Assert RD and read (Phase Error (PE) MSW; PE LSW; False Lock (FL) MSW; FL LSW).
LKINT
SR-7
A0-2
C0-7
CLK
WR
RD
1
2
3-30
5
3
3
FIGURE 24. PROCESSOR INTERRUPT MONITOR/LOCK DETECTOR READ
dec
dec
dec
A0-2
C7-0
4
CLK
RD
to enable the Lock Detector Phase Error Accumulator for Reading.
to initialize the Lock Detector Accumulators and Reset Integration Counters. (Only has an effect in P
to restart the Lock Detector. (Only necessary if not in the P mode).
FIGURE 25. INTERNAL STATUS REGISTER READ
5
3
PE
STATUS CAN CHANGE EVERY CLK
MSW
6
4
HSP50210
2
5
PE
LSW
6
1
5
FL
MSW
6
0
5
FL
LSW
7
30
8
4
9
25
10
4