k4d263238m-qc60 Samsung Semiconductor, Inc., k4d263238m-qc60 Datasheet - Page 10

• Manufacturer Part Number: k4d263238m-qc60
• Description: 1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
• Manufacturer: Samsung Semiconductor, Inc.

K4D263238M
EXTENDED MODE REGISTER SET(EMRS)
default value of the extended mode register is not defined, therefore the extend mode register must be written after power
up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high
on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going
low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-
ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The
BA
RFU
1
* RFU(Reserved for future use)
should stay "0" during EMRS
cycle.
BA
BA
0
1
1
0
0
A
EMRS
A
11
MRS
n
~ A
0
A
10
RFU
A
9
0
1
A
A
6
Figure 7. Extend Mode Register set
8
1
1
A
1
A
Matched impedance 30% of full drive strength
7
Output Driver Impedance Control
D.I.C
Weak
A
6
- 10 -
A
5
60% of full drive strength
A
4
RFU
A
3
A
2
128M DDR SDRAM
D.I.C
A
1
Rev. 1.3 (Aug. 2001)
A
0
1
DLL
A
0
0
DLL Enable
Address Bus
Extended
Mode Register
Disable
Enable