k4d263238m-qc60 Samsung Semiconductor, Inc., k4d263238m-qc60 Datasheet - Page 3

• Manufacturer Part Number: k4d263238m-qc60
• Description: 1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
• Manufacturer: Samsung Semiconductor, Inc.

K4D263238M
Revision 1.0 (December 13, 2000)
• Defined capacitance values
• Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK
Revision 0.5 (December 8, 2000)
• Changed AC input level from Vref + 0.31V to Vref + 0.35V
• Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based.
•
Revision 0.4 (November 29, 2000) - Preliminary
• Removed K4D263238M-QC40
• Several AC parameters of K4D263238M-QC45 have been changed
• Several AC parameters of K4D263238M-QC50 have been changed
• Several AC parameters of K4D263238M-QC55 have been changed
• Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns
• Add DC Characteristics value
•
• Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us.
•
Revision 0.3 (June 8, 2000)
• Removed Block Write function
Revision 0.2 (April 10, 2000)
• Separated tRCD into tRCDRD and tRCDWR
Revision 0.1 (March 16, 2000)
• Define the spec based on Vdd&Vddq=2.5V
• Maximum target frequency upto 250MHz@CL4
•
Revision 0.0 (December 27, 1999) - Target Spec
• Defined Target Specification
Removed Write Interrupt by Read function
Changed V
Define V
Changed I
- tRCDRD: Row to Column delay for READ
- tRCDWR: Row to Column delay at WRITE
- Changed tDQSCK & tAC from 0.6ns to 0.75ns
- Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns
- Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns.
- Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK
- Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns
- Corrected tDAL from 5tCK to 6tCK
- Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Corrected tDAL from 5tCK to 6tCK
- Changed tDQSQ from 0.45ns to 0.5ns. Changed tOH from tHP-0.6ns to tHP-0.5ns.
IH
(max) / V
IL
IN
,I
OL
/V
OUT
test condition from 0V< V
/V
IL
(min) as a note in Power & DC operating Condition table
DDQ
in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V.
IN
<V
DD
+0.3V to 0V< V
- 3 -
IN
<V
DD
.
128M DDR SDRAM
Rev. 1.3 (Aug. 2001)