k4d263238m-qc60 Samsung Semiconductor, Inc., k4d263238m-qc60 Datasheet - Page 9

• Manufacturer Part Number: k4d263238m-qc60
• Description: 1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
• Manufacturer: Samsung Semiconductor, Inc.

K4D263238M
MODE REGISTER SET(MRS)
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
addressing mode uses A
used for DLL reset. A
for various burst length, addressing modes and CAS latencies.
* RFU(Reserved for future use)
RFU
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
BA
should stay "0" during MRS
cycle.
MRS Cycle
BA
Command
0
1
1
CK, CK
0
BA
0
0
*1: MRS can be issued only at all banks precharge state.
*2: Minimum
EMRS
A
MRS
0
n
~ A
DLL
~ A
A
11
A
0
1
11
0
8
7,
and BA
A
NOP
8
RFU
A
3
, BA
DLL Reset
t
, CAS latency(read latency from column address) uses A
10
RP
Yes
No
0
is required to issue MRS command.
0
0
, BA
and BA
Precharge
All Banks
A
9
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
1
1
DLL
must be set to low for normal MRS operation. Refer to the table for specific codes
CAS Latency
A
8
A
0
0
0
0
1
1
1
1
Test Mode
6
NOP
A
0
1
7
TM
A
0
0
1
1
0
0
1
1
A
2
5
7
t
RP
Normal
A
0
1
0
1
0
1
0
1
Test
mode
NOP
4
A
6
CAS Latency
- 9 -
3
Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A
3
4
5
MRS
4
A
4
Burst Length
t
MRD
NOP
A
0
0
0
0
1
1
1
1
Burst Type
2
=2 t
BT
A
A
0
1
5
3
3
CK
A
0
0
1
1
0
0
1
1
4
1
Command
~ A
Sequential
Interleave
A
Any
A
0
1
0
1
0
1
0
1
128M DDR SDRAM
2
6
Burst Length
Type
0
. A
6
7
Sequential
Full page
is used for test mode. A
A
Reserve
Reserve
Reserve
Reserve
1
NOP
Rev. 1.3 (Aug. 2001)
2
4
8
Burst Type
7
A
0
NOP
Address Bus
Interleave
Register
Reserve
Reserve
Reserve
Reserve
Reserve
Mode
8
2
4
8
0
~ A
8
2
is
,