k4d263238m-qc60 Samsung Semiconductor, Inc., k4d263238m-qc60 Datasheet - Page 15

• Manufacturer Part Number: k4d263238m-qc60
• Description: 1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
• Manufacturer: Samsung Semiconductor, Inc.

K4D263238M
tQH Timing (CL3, BL2)
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle
- tQHmin = tHP-X where
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
COMMAND
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
variation and replaces tDV
output valid window even then the clock duty cycle applied to the device is better than 45/55%
strobe and all data associated with that data strobe are coincidentally valid.
CK, CK
DQS
DQ
CS
READA
0
1
1
2
- 15 -
tDQSQ(max)
3
Da0
tQH
tHP
tDQSQ(max)
Da1
4
128M DDR SDRAM
Rev. 1.3 (Aug. 2001)
5